Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input path

Aghaee, Toktam; Biabanifard, Sadegh; Golmakani, Abbas

doi:10.1007/s10470-016-0874-2

Cited by 40 publications

(17 citation statements)

References 9 publications

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“…Usually, cascode amplifiers are more stable; however, they have circuit complexity and suffer from low voltage swings. This stems from the fact that advanced CMOS technology exploits lower supply voltages, which limits the Cascode circuit's performance [1–3]. Therefore, as a compatible design, multi‐stage amplifiers are considered extensively.…”

Section: Introductionmentioning

confidence: 99%

Four‐stage CMOS amplifier: frequency compensated using differential block

Daryan

Khalesi

Ghods

2020

IET Circuits, Devices & Systems

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Section: Introductionmentioning

confidence: 99%

Four‐stage CMOS amplifier: frequency compensated using differential block

Daryan

Khalesi

Ghods

2020

IET Circuits, Devices & Systems

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“…We know that over the past years, because of technology advancements, the supply voltage has undergone major reduction without any significant intervention on threshold voltage. So cascode structures are not compatible with low‐supply voltages and submicron fabrication, while multistage structures provide high direct current (DC) gain easily . We also know that a multistage amplifier with frequency compensation network is immensely complicated and that everything is in some way connected.…”

Section: Introductionmentioning

confidence: 99%

“…So cascode structures are not compatible with low-supply voltages and submicron fabrication, while multistage structures provide high direct current (DC) gain easily. [10][11][12][13][14][15][16] We also know that a multistage amplifier with frequency compensation network is immensely complicated and that everything is in some way connected. Additionally, because of design simplicity, many assumptions are considered to more simple statements.…”

mentioning

confidence: 99%

A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

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“…Numerous techniques are presented and discussed in details to increase DC gains such as exploiting cascode structures and multistage amplifiers. While cascode approach is not compatible with low voltage operation due to voltage swing reduction . And also more importantly multistage designs need frequency compensation to avoid instability issues …”

Section: Introductionmentioning

confidence: 99%

Nonlinear current source charge scheme for comparator based switched capacitor integrator

Valianpour¹,

Chaharmahali

Biabanifard³

2019

Int J Numerical Modelling

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The continuous development of complementary metal-oxide-semiconductor (CMOS) technology makes it difficult to design high speed and low power amplifiers. One of the appropriate alternatives is comparator-based circuits.In this paper, a modified structure for comparator-based switched-capacitor integrator is presented. This structure increases the clock frequency considerably by using a nonlinear current source. The proposed integrator involves replacing the two linear current sources in conventional comparator-based switched-capacitor integrator with just one nonlinear current source. Also, the new logic part is presented, which reduces the circuit size and power dissipation consequently. The suggested circuit reduces integration dependency to the logic part while decreases charge transfer phases to just a single phase. According to the proposed structure, a first order comparator-based switched-capacitor integrator is designed in 0.18 μm complementary metaloxide-semiconductor technology with a 100 MHz as the clock frequency.

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Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input path

Cited by 40 publications

References 9 publications

Four‐stage CMOS amplifier: frequency compensated using differential block

Four‐stage CMOS amplifier: frequency compensated using differential block

A high‐performance CMOS four‐stage amplifier

Nonlinear current source charge scheme for comparator based switched capacitor integrator

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