Nonlinear current source charge scheme for comparator based switched capacitor integrator

Abstract

The continuous development of complementary metal-oxide-semiconductor (CMOS) technology makes it difficult to design high speed and low power amplifiers. One of the appropriate alternatives is comparator-based circuits.In this paper, a modified structure for comparator-based switched-capacitor integrator is presented. This structure increases the clock frequency considerably by using a nonlinear current source. The proposed integrator involves replacing the two linear current sources in conventional comparator-based switched-capacitor integrator with just one nonlinear current source. Also, the new logic part is presented, which reduces the circuit size and power dissipation consequently. The suggested circuit reduces integration dependency to the logic part while decreases charge transfer phases to just a single phase. According to the proposed structure, a first order comparator-based switched-capacitor integrator is designed in 0.18 μm complementary metaloxide-semiconductor technology with a 100 MHz as the clock frequency.

Four stage CMOS operational amplifier, frequency compensated via active miller network

“…1,2 Smaller supply voltages limit exploiting cascode structures since evolved MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) need considerable Drain-Source voltage to operate in the saturation region. 3,4 This is the main cause of using multi-stage amplifiers while cascode structures are more efficient, stable, simple, and low-power. Nevertheless, multi-stage or cascade amplifiers turn to reliable choices, providing a very large DC gain, more than 100 dB.…”

“…This becomes a challenging task for circuit designers since supply voltages are reduced continuously by advancing technology 1,2 . Smaller supply voltages limit exploiting cascode structures since evolved MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) need considerable Drain‐Source voltage to operate in the saturation region 3,4 . This is the main cause of using multi‐stage amplifiers while cascode structures are more efficient, stable, simple, and low‐power.…”

Four‐stage CMOS operational transconductance amplifier: Compensated via double differential blocks

“…So, exploiting frequency compensation methods becomes an inevitable task to achieve stable amplification, at least conditionally. [8][9][10][11] In this regard, numerous frequency compensation approaches are reported by scientists, mainly for three-stage amplifiers. It should be noted that two-stage structures can be frequency compensated via a single Miller capacitor and available DC-gain is limited to less than 100 dB.…”

“…But the problem turns to stability issues due to the increasing number of nods, knowing that each node poses a pair of pole‐zero to the system. So, exploiting frequency compensation methods becomes an inevitable task to achieve stable amplification, at least conditionally 8–11 . In this regard, numerous frequency compensation approaches are reported by scientists, mainly for three‐stage amplifiers.…”

Four‐stage CMOS amplifier design based on symbolic calculations: Stack comparison approach

“…However, the above operators do not consider these correlations. (2) The simple replacement of circuit parameters with corresponding ranges and the use of high operators give rise to very wide sentences variation and polynomials, which have been taken too carefully 10‐13 . For example, for one parameter in some sentences the maximum range is set, whereas for the same parameter in other sentences the minimum value is set.…”