Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm<sup>2</sup> 6T-SRAM bitcell

Fenouillet-Béranger, C.; Denorme, S.; Icard, B.; Bœuf, F.; Coignus, J.; Faynot, O.; Brévard, L.; Buj, C.; Soonekindt, C.; Todeschini, J.; Le-Denmat, Jean-Christophe; Loubet, N.; Gallon, C.; Perreau, P.; Manakli, S.; Mmghetti, B.; Pain, Laurent; Arnal, V.; Vandooren, A.; Aime, D.; Tosti, L.; Savardi, C.; Martín, F.; Salvetat, T.; Lhostis, S.; Laviron, C.; Auriac, N.; Kormann, T.; Chabanne, G.; Gaillard, S.; Belmont, O.; Laffosse, E.; Barge, D.; Zauner, A.; Tarnowka, A.; Romanjec, K.; Brut, H.; Lagha, A.; Bonnetier, S.; Joly, Frédéric; Mayet, N.; Cathignol, A.; Galpin, D.; Pop, D.; Delsol, R.; Pantel, R.; Pionnier, F.; Thomas, G.D.; Bensahel, D.; Deleombus, S.; Skotnicki, T.; Mmgam, H.

doi:10.1109/iedm.2007.4418919

Cited by 43 publications

(39 citation statements)

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“…UTBB-FDSOI is considered as one of the best solution to overcome conventional planar Bulk CMOS limitations [1][2][3]. Thanks to an excellent electrostatic control and transport properties, this architecture is suitable to reach ITRS requirements for 28 nm technology node and beyond [4].The threshold voltage can be easily adjusted by applying back biases (VB) and it has recently been demonstrated that the mobility can be enhanced in the forward regime (VB > 0 V for nMOS and VB < 0 V for pMOS) [5].…”

Section: Introductionmentioning

confidence: 99%

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

et al. 2013

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scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility. Journal of Computational Electronics, Springer Verlag, 2013, 12, pp.675-684. 10.1007 Multi-scale analysis of the mobility in high-k UTBB-FDSOI Devices and comparison to split-CV measurements. Abstract-A rigorous study of the mobility in high-k metal gate Ultra-Thin Body and Box Fully Depleted SOI (UTBB-FDSOI) devices is done by means of split C-V measurements and advanced simulations. Measurements have been performed for various Interfacial Layer (IL)Equivalent Oxide Thickness (EOT) allowing an investigation of the physical mechanisms responsible for the mobility degradation at high-k/IL interface. The impact of the back bias on transport properties is investigated and mobility enhancement in the forward regime (back gate inversion) is demonstrated. A multi-scale simulation approach is performed and we compared simulated mobility using quantum Non-Equilibrium Green's Functions (NEGF) to semi-classical solvers results using the Kubo Greenwood (KG) approach. We demonstrated good correlations between these solvers comparing phonon and remote Coulomb-limited mobility. However, a clear overestimation of the surface roughnesslimited mobility determined using semi-classical solvers is shown compared to NEGF results. These advanced solvers have been used to reproduce mobility measurements allowing us to calibrate Technology computer aided design (TCAD) mobility models.

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Section: Introductionmentioning

confidence: 99%

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

et al. 2013

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“…At 300 mm and the sub-32-nm node level low standby power devices are being achieved, and exhibit leakage current as low as 6.6 pA/µm. This allows for the fabrication of low standby power 6T SRAMs [23] (Figure 1). Such a metric for FDSOI is possible because of the excellent control of ultra-thin undoped silicon layer thickness ( Figure 2) on large wafer diameters at a large volume production level [24].…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

“…(TiN/HfSiON) can be integrated on 300 mm wafers based on finding from collaborative research. 32 nm design rules: LSTP 6T SRAM in an industrial environment (Lg=25 nm n and p MOS show I off =6 pA/µm @VDD=1.1 V)[23].…”

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confidence: 99%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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“…The combination of a midgap/high-k metal gate stack with this type of undoped channels devices enable to greatly improve variability [1][2][3] compared to bulk technology while keeping suitable n-channel and p-channel threshold voltage (Vth) for low power applications. In FDSOI devices, the better control of SCE is mainly attributed to the thinness of the silicon film.…”

Section: Introductionmentioning

confidence: 99%

Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

Fenouillet-Béranger

Perreau

Denorme³

et al. 2010

Solid-State Electronics

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Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell

Cited by 43 publications

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Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Ultra-thin films and multigate devices architectures for future CMOS scaling

Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

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Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell

Cited by 43 publications

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Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Ultra-thin films and multigate devices architectures for future CMOS scaling

Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

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Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell