Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

Fenouillet-Béranger, C.; Perreau, P.; Denorme, S.; Tosti, L.; Andrieu, F.; Weber, O.; Monfray, S.; Barnola, S.; Arvet, C.; Campidelli, Y.; Haendler, S.; Beneyton, R.; Perrot, C.; Buttet, C. de; Gros, P.; Pham-Nguyen, Loan; Leverd, F.; Gouraud, P.; Abbate, F.; Baron, F. A.; Torres, A.; Laviron, C.; Pinzelli, L.; Vetier, J.; Borowiak, C.; Margain, A.; Delprat, D.; Boedt, F.; Bourdelle, K.K.; Nguyen, Bich‐Yen; Faynot, O.; Skotnicki, T.

doi:10.1016/j.sse.2010.04.009

Cited by 46 publications

(5 citation statements)

References 6 publications

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“…The Fully Depleted (FD) SOI MOSFET with Ultra Thin Buried Oxide (UTBOX) is considered as one of the best candidates for the sub 32nm technology nodes due to the better short channel effect maintaining the well known planar structure (1).…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Silicon Film Thickness and the Ground Plane Influence on Ultra Thin Buried Oxide SOI nMOSFETs

et al. 2012

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This paper presents an analysis of the Ground Plane (GP) implantation and silicon film thickness influences on Ultra Thin Buried Oxide (UTBOX) SOI MOSFETs. The results obtained experimentally and by simulations, considering the GP implantation, show that the device must have a GP implantation higher than 1x10 18 cm -3 in order to eliminate the substrate effect. In spite of the fact that the substrate influence on the drain current is negligible with a high GP concentration, the coupling between front and back interface increases for thinner silicon films.

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Section: Introductionmentioning

confidence: 99%

Analysis of the Silicon Film Thickness and the Ground Plane Influence on Ultra Thin Buried Oxide SOI nMOSFETs

et al. 2012

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“…Ground planes structures. The advantages of implementing ground-plane (GP) in the substrates of the UTBB SOI MOSFETs structures in managing SCEs have been reported in many literatures [6], [9]- [11]. With the implementation of GP, the depletion extending under the buried oxide can be suppressed, resulted in outstanding electrostatic control with reduction of DIBL, subthreshold swing (SS) and variability.…”

Section: Short-channel Effects (Sces)mentioning

confidence: 99%

Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review

Othman

Arshad

Sabki

et al. 2015

AMR

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This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

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“…The Ultra-Thin Body and Buried oxide Silicon-On-Insulator technology is largely used for the microelectronic industries as a mainstream technology [1]. In this technology, smaller and smaller devices are being developed and fabricated in order to increase the density of the integrated circuits from 28 nm technology nodes down to 14 nm [2,3]. The geometry of the devices has been developed along the years and the nanowire (NW) gate-all-around (GAA) is a good candidate for a sub 10 nm technology node.…”

Section: Introductionmentioning

confidence: 99%

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Itocazu

Almeida

Sonnenberg

et al. 2019

Semicond. Sci. Technol.

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This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW =10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW =220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec −1 (W NW =10 nm) to 68 mV dec −1 (W NW =220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec −1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

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Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

Cited by 46 publications

References 6 publications

Analysis of the Silicon Film Thickness and the Ground Plane Influence on Ultra Thin Buried Oxide SOI nMOSFETs

Analysis of the Silicon Film Thickness and the Ground Plane Influence on Ultra Thin Buried Oxide SOI nMOSFETs

Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

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