Full wafer integration of NEMS on CMOS by nanostencil lithography

Abstract

Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nanodevices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around 1.5 MHz were measured in air and vacuum and tuned by applying dc voltages of 10V and 1V respectively.

Compact CMOS current conveyor for integrated NEMS resonators

“…Following the proposals of Sections 3 and 4, a compact 1.5MHz NEMS resonator together with the CMOS interfacing circuit has been integrated through the in-house standard CMOS double polysilicon technology and the full-wafer post-processing steps based on nanostencil lithography described in [9]. As shown in Figure 5, the resulting size of the complete mixed electromechanical circuit without pads is around 800µm×400µm (0.32mm 2 ).…”

“…However, the novelty here is the lithography technique employed for patterning the nanodevices: an enhanced resolution down to 200nm and full-wafer parallel processing are obtained [9] by applying nanostencil lithography (nSL) [7]. In this new process, and after concluding the fabrication of the CMOS circuits, nanodevice areas are selectively patterned with a 80nm thick aluminum layer by nSL.…”

“…Secondly, the NEMS current sensed by M4 is amplified by the geometry scaling factors 5,6 and N = (W/L) 11,12 (W/L) 9,10 of the two-stage cascode current mirrors M5-M8 and M9-M12 biased at V casp and V casn , respectively. In order to reduce the overall power consumption, a K/M fraction of the biasing is subtracted before the second amplification stage.…”

“…From a technological point of view, the NEMS fabrication is based on nanostencil lithography [7], while from the design side a new low-power CMOS interface topology is proposed based on second generation current conveyors (CCII) [8]. Finally, the mixed electro-mechanical system is fully integrated through a combination of in-house standard CMOS technology and nanodevice post-processing [9].…”

Sub-100 nm-scale aluminum nanowires by stencil lithography: Fabrication and characterization

“…1) [11]. Recently, SL was used to fabricate sub-micron resonators on CMOS circuits [12], showing the capability of the technique for high resolution patterning and its integration into current microelectronic fabrication methods. The stencils can also be used multiple times, offering a potentially low-cost, efficient and reusable tool [13].…”