Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 µm long have been achieved showing a resistivity of 10 µΩcm for Al and 5 µΩcm for Au and maximum current density of ∼10 8 A/cm 2 . This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale.An important objective in nanotechnology is the development of alternative nanopatterning methods and the fabrication of novel nanoscale structures and materials. Among such structures, nanowires (NWs) have shown potential and applications in a broad range of fields such as electronics, 1,2 magnetic memories, 3 thermoelectric, 4,5 nanomechanical, 6 optoelectronic, 7 and biosensing devices 8-10 due to their physical properties and surface to volume ratio. In particular, metallic nanowires can be applied for interconnects, magnetic memories based on spin-polarized current 3 and biosensors. 9 To fabricate NWs, the two approaches used are the chemical synthesis (bottom-up) and the nanopatterning methods (topdown).
A tool and method for flexible and rapid surface patterning technique beyond lithography based on high-resolution shadow mask method, or nanostencil, is presented. This new type of miniaturized shadow mask is fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. Thereby apertures in a 100-500 nm thick low-stress silicon nitride membrane in the size range from , 100 nm to . 100 mm were made. The stencil device is mechanically fixed on the surface and used as miniature shadow mask during deposition of metal layers. Using this method, aluminum micro-and nanostructures as small as 100 nm in width were patterned. The deposited micro-and nano-scale structures were used as etch mask and transferred into a sub-layer (in our case silicon nitride) by dry plasma etching. High-resolution shadow masking can be used to create micro / nanoscale patterns on arbitrary substrates including mechanically fragile or chemically active surfaces.
Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.
We achieved parallel nanoscale patterning of ferroelectric complex oxides by pulsed laser deposition through a nanostencil ͑i.e., through a pattern of apertures in a thin free-standing membrane͒. Ordered arrays of nanostructured barium titanate ͑BaTiO 3 ͒ were obtained onto different substrates in a single deposition step, at room temperature, replicating accurately the aperture patterns in the stencil membrane. After a postdeposition annealing treatment, x-ray diffraction pattern showed a nanocrystalline BaTiO 3 structure close to the perovskite cubic phase with grains 30-35 nm in size. Their local ferroelectric properties were detected using piezoresponse force microscopy.
One of the major advantages of stencil lithography is the possibility to use stencils many times. However, when stencils contain nanoapertures, the clogging of the membranes limits the useful life time of the stencils. The clogging is due to the accumulation of material deposited inside the apertures of the stencil. Here, we report a study on the effect of the clogging on the life time of stencils after Al depositions through the stencils. Then we present a method to clean the stencils based on Al wet etching to eliminate the clogging. We show that this method allows the reusability of stencils for the repeatable depositions of Al nanostructures.
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