From poly line to transistor: building BSIM models for non-rectangular transistors

Poppe, Wojtek J.; Capodieci, Luigi; Wu, Joanne; Neureuther, Andrew R.

doi:10.1117/12.657051

Cited by 47 publications

(32 citation statements)

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“…There have been several approaches to electrically model non-rectilinear geometries [7][8][9][10][12][13][14]. All of these works consider the threshold voltage and hence the current density to be uniform along the device width.…”

Section: Introductionmentioning

confidence: 99%

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Jeong

Kahng

Samadi

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the I on and I o f f impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ∆I on and ∆I o f f . Finally, the electrical metric for line-end printing is defined as expected change in I on or I o f f under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.

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Section: Introductionmentioning

confidence: 99%

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Jeong

Kahng

Samadi

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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“…Different from previous works [8][9][10] which use EGLs to replace original values of uniform gate lengths in SPICE simulation, our post-litho device modeling card can more precisely simulate the impact of length variations within a single gate by continuously modifying the source/drain current.…”

Section: Post-litho Device Modeling Cardmentioning

confidence: 99%

“…As the non-rectangular of channel shape is most directly decided by the gate shape, the nonrectangular gate can be directly used to predict the channel shape. Recent works [8][9][10] use gate slicing and equivalent gate length (EGL) methods to simulate the impact of non-rectangular gate shapes in SPICE which is much faster than TCAD software. Two EGLs of each device are defined to replace the original uniform gate length set on layout: ON EGL for timing issues when the device is turned on and OFF EGL for leakage issues when the device is cutoff.…”

Section: Introductionmentioning

confidence: 99%

“…Another limitation of these EGL works [8][9][10] is that they only studied the performance difference between non-rectangular and ideal rectangular gates. In fact, device models, such as BSIM3, BSIM4 [11], and PTM [12], and their parameters are extracted from the real devices with certain non-rectangular shapes.…”

Section: Introductionmentioning

confidence: 99%

“…In fact, device models, such as BSIM3, BSIM4 [11], and PTM [12], and their parameters are extracted from the real devices with certain non-rectangular shapes. So the impact of gate shape with certain non-rectangles on device performance has been already included in the device models [10]. Performance simulations of gates between different nonrectangular shapes are necessary and crucial, or the impact of nonrectangular gate shape may be overestimated.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A unified non-rectangular device and circuit simulation model for timing and power

Shi

Pan

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit characterizations for the post-OPC non-ideal-shape wafer images, with significant impacts on timing and power. Most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. In this paper, we propose a unified post-litho device characterization model and circuit simulation for timing and power. To our best knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. Based on this method, the parameter extraction is also included in the model which was omitted by previous works. A post-litho model card is proposed for circuit simulation to combine these two techniques. Our experimental results validate the new model.

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Design for manufacturing meets advanced process control: A survey

Pan

Cho

et al. 2008

Journal of Process Control

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From poly line to transistor: building BSIM models for non-rectangular transistors

Cited by 47 publications

References 0 publications

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Quantified Impacts of Guardband Reduction on Design Process Outcomes

A unified non-rectangular device and circuit simulation model for timing and power

Design for manufacturing meets advanced process control: A survey

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