Optical proximity correction (OPC) is one of the most widely used Resolution Enhancement Techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process conditions without considering process variations because of the lack of variational lithography models. A simple method to improve OPC results under process variations is to sample multiple process conditions across the process window, which requires long runtime. We derive a variational lithography model (VLIM) which can simulate across the process window without much runtime overhead compared to the conventional lithography models. To match the model to experimental data, we demonstrate VLIM calibration method. The calibrated model has accuracy comparable to non-variational models, but it has the advantage of taking process variations into consideration. We introduce the variational edge placement error (V-EPE) metrics based on the model, a natural extension to the edge placement error (EPE) used in conventional OPC algorithms. A true process-variation aware OPC (PV-OPC) framework is proposed using the V-EPE metric. Due to the analytical nature of VLIM, our PV-OPC is only about 2-3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. Thus our post PV-OPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process parameters without considering process variations, due to prohibitive runtimes of lithography simulations across process windows. This is the first paper to propose a true process-variation aware OPC (PV-OPC) framework. It is enabled by the variational lithography modeling and guided by the variational edge placement error (V-EPE) metrics. Due to the analytical nature of our models, our PV-OPC is only about 2-3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (dosage and focus) during OPC. Thus our post PV-OPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.
For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit characterizations for the post-OPC non-ideal-shape wafer images, with significant impacts on timing and power. Most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. In this paper, we propose a unified post-litho device characterization model and circuit simulation for timing and power. To our best knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. Based on this method, the parameter extraction is also included in the model which was omitted by previous works. A post-litho model card is proposed for circuit simulation to combine these two techniques. Our experimental results validate the new model.
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