Design for manufacturing meets advanced process control: A survey

Pan, David Z.; Yu, Peng; Cho, Minsik; Ramalingam, Anand; Kim, Kiwoon; Rajaram, Anand; Shi, Sean X.

doi:10.1016/j.jprocont.2008.04.007

Cited by 10 publications

(3 citation statements)

References 120 publications

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“…Ip(x, y; F ) for different random values of F (F 's statistical distribution can be characterized by standard methods in DesignFor-Manufacturability DFM [11]) are computed by a simulation model that employs Eqns.…”

Section: Optimization Algorithmmentioning

confidence: 99%

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction

Forte

Srivastava

2012

Proceedings of the 49th Annual Design Automation Conference

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Physically Unclonable Functions (PUFs) are effective for security applications because they generate unique signatures that are resistant to cloning attempts as well as physical tampering. A silicon PUF is a special circuit embedded in an IC that relies on random fabrication process variations to produce a unique signature for its native IC. While current research directions have focused on improving PUF quality at the architectural level, little work has explicitly targeted their fundamental source of randomness, the fabrication process. During IC fabrication, Optical Proximity Correction (OPC) is typically used to suppress manufacturing variations. In this paper, we recognize that this is actually counterintuitive for PUFs. We provide a novel framework which enables OPC to increase the effects of manufacturing variations within PUF circuitry and produce more randomness in PUFs for greater uniqueness and reliability. The proposed OPC techniques are validated using a population of 100 ring oscillator PUFs. Results show that our schemes provide over five times larger variation in ring oscillator delay, improve PUF uniqueness by 5%, and improve PUF reliability by as much as 70% when compared to conventional OPC.

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Section: Optimization Algorithmmentioning

confidence: 99%

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction

Forte

Srivastava

2012

Proceedings of the 49th Annual Design Automation Conference

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“…For sub-20nm technology nodes, the conventional transistor and lithography scaling purely relying on the tool and material development has hit significant difficulties [1][2][3][4][5][6][7] . Other avenues such as alternative device architecture, asymmetric pitch scaling, emerging material had to be exploited to achieve power/performance/area/cost (PPAC) scaling targets without shrinking design rules by a 0.7X factor.…”

Section: Introductionmentioning

confidence: 99%

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

et al. 2016

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In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the desired features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

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“…Hence, design for manufacturing(DFM) [2] is proposed to meet advanced process control. Under different optical proximity effects(OPEs) including corner rounding, pulling back at the end of the narrow line, the wide variation of line widths and layout-dependent variations, some related algorithms [3][4][5][6] were proposed to minimize the clock skew in a variation-aware clock tree.…”

Section: Introductionmentioning

confidence: 99%

Post-layout OPE-predicted redundant wire insertion for clock skew minimization

Yan

Chen

2012

2012 IEEE 30th International Conference on Computer Design (ICCD)

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Based on the equilibrium concept of inserting load in a physical balance, the insertion of redundant wires can be used to minimize the clock skew in an OPE-predicted clock tree. For five tested benchmarks, the experimental results show that our proposed algorithm only increases 2.8% of the total load on the average for the insertion of OPE-predicted redundant wires and decreases 30.85 ps of the clock skew on the average to obtain the near zero-skew result in reasonable CPU time. 504 978-1-4673-3052-7/12/$31.00 ©2012 IEEE

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Design for manufacturing meets advanced process control: A survey

Cited by 10 publications

References 120 publications

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Post-layout OPE-predicted redundant wire insertion for clock skew minimization

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