FPGA Prototyping Strategy for a H.264/AVC Video Decoder

Rosa, Vagner Santos da; Staehler, Wagston Tassoni; Azevedo, Arnaldo; Porto, Roger; Agostini, Luciano; Bampi, Sérgio; Susin, Altamiro

doi:10.1109/rsp.2007.23

Cited by 5 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Examples of prior studies in the second category include [2]- [3][4] [5] . The study in [2] presented implementations of IQIT, intra prediction, inter prediction, and deblocking modules. However, they did not report implementations of the entropy decoder or frame buffer.…”

Section: Related Workmentioning

confidence: 99%

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

Barge

Ababei

2017

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

different implementations. The first implementation uses a 3×3 network-on-chip and is validated on the DE4 development board, which uses Altera's Stratix IV GX FPGA chip. The second implementation uses a 2×2 network-on-chip and is validated on the Cyclone V SoC FPGA, which is a smaller FPGA chip available on the DE1-SoC board. Both implementations will be released to the public domain with the hope that they will foster further research, in addition to facilitating replication and comparison to our results. SECTION I.

show abstract

Section: Related Workmentioning

confidence: 99%

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

Barge

Ababei

2017

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

show abstract

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Zhang

Zhou

Goto

2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

View full text Add to dashboard Cite

Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-Verification

Katona

Djukaric

Cvejanovic

2009

2009 First IEEE Eastern European Conference on the Engineering of Computer Based Systems

View full text Add to dashboard Cite

This paper addresses problems associated with verification and FPGA prototyping platform preparation for the pre-silicon software development. Increasing the size of modern SoC makes traditional approach of mapping entire design into one FPGA unsuitable. Consequently, other more appropriate scheme must be found in order to achieve optimal results. One solution for the problem could be platforms with 16 or more modern FPGAs. However, such platform verification cost would be significantly increased and most of the SoC designs would face serious issues during platform preparation if design concept is not adjusted to the specific verification process. In this paper we propose a new approach for multiple FPGA platform scheme suitable for today's rapid growth of SoC ASIC designs. The proposed approach targets the modular verification approach for pre-silicon software verification instead of using the full scale system verification process.

show abstract

FPGA Prototyping Strategy for a H.264/AVC Video Decoder

Cited by 5 publications

References 11 publications

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-Verification

Contact Info

Product

Resources

About

FPGA Prototyping Strategy for a H.264/AVC Video Decoder

Cited by 5 publications

References 11 publications

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

Live demonstration: FPGA based 3840&#x00D7;2160 video decoding and displaying system

Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-Verification

Contact Info

Product

Resources

About

Live demonstration: FPGA based 3840×2160 video decoding and displaying system