Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-Verification

Abstract

This paper addresses problems associated with verification and FPGA prototyping platform preparation for the pre-silicon software development. Increasing the size of modern SoC makes traditional approach of mapping entire design into one FPGA unsuitable. Consequently, other more appropriate scheme must be found in order to achieve optimal results. One solution for the problem could be platforms with 16 or more modern FPGAs. However, such platform verification cost would be significantly increased and most of the SoC designs would face serious issues during platform preparation if design concept is not adjusted to the specific verification process. In this paper we propose a new approach for multiple FPGA platform scheme suitable for today's rapid growth of SoC ASIC designs. The proposed approach targets the modular verification approach for pre-silicon software verification instead of using the full scale system verification process.