H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

Abstract

different implementations. The first implementation uses a 3×3 network-on-chip and is validated on the DE4 development board, which uses Altera's Stratix IV GX FPGA chip. The second implementation uses a 2×2 network-on-chip and is validated on the Cyclone V SoC FPGA, which is a smaller FPGA chip available on the DE1-SoC board. Both implementations will be released to the public domain with the hope that they will foster further research, in addition to facilitating replication and comparison to our results. SECTION I.

Digital Image Decoder for Efficient Hardware Implementation

“…The proposed solution for digital image decoder can process 5.1 times larger frame/tile size than [ 5 ] but utilizes only 15% more memory resources. Finally, the proposed digital image decoder architecture can process 32.4 times larger frame size, while requires only 64% greater memory size in comparison with 2 × 2 NoC decoder from [ 10 ]. In comparison to all other state-of-the-art solutions, the proposed architecture requires less memory size although it can process larger frame size.…”

“…Hardware implementation of a full HD capable H.265/HEVC video decoder, presented in [ 9 ], targeted constraints related to hardware costs. Video decoder implemented on FPGAs using 3 × 3 and 2 × 2 networks-on-chip, with communication between the decoder modules performed via a network-on-chip, has been described in [ 10 ].…”

International Journal of Electronics and Telecommunications

“…The key components of the bitstream parser path include Heading One Detector, context adaptive variable length codes (CAVLC) decoder, Exponential Golomb decoder, and Fixed Length decoder, where they are all in charge of reverse coded syntax elements and then extracts quantized transform coefficients and prediction information. The reconstruction data path consists of Intra Prediction, Inter Prediction, and deblocking Filter [6].…”