FPGA Design of A H.264/AVC Main Profile Decoder for HDTV

Agostini, Luciano; Filho, Azevedo; Rosa, Vagner Santos da; Berriel, E.A.; Santos, Tatiana G. S. dos; Bampi, Sérgio; Susin, Altamiro

doi:10.1109/fpl.2006.311258

Cited by 14 publications

(5 citation statements)

References 9 publications

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“…For this experiment the target device was a Xilinx XC2VP30). In other to compose a multi-encoder solution, it was selected two works, which have been designed to support efficiently a HD single layer application [12] [13]. Each work optimizes one path of the H.264 intra computation coding (forward or inverse respectively).…”

Section: Resultsmentioning

confidence: 99%

Efficient hardware solution for practical intra h.264/SVC video encoder implementation

Hüsemann

Susin

Roesler

et al. 2011

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design

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The emergent standard H.264/SVC (scalable video coding) combines distinct complex techniques in order to allow efficient data compression considering data among consecutive layers. In practice, a complete implementation of this scalable encoder is not trivial, since the global complexity increases proportionally with the number of layers involved. Considering that, this paper proposes an innovative scalable architecture, which adopts a flexible approach able to reuse computational hardware modules in order to perform iteratively the SVC intra computational coding, for both the base layer and enhancement layers. In order to validate this proposal it was implemented in VHDL and compared with other conventional hardware approaches, confirming significant gain in terms of occupied memory and total chip area.

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Section: Resultsmentioning

confidence: 99%

Efficient hardware solution for practical intra h.264/SVC video encoder implementation

Hüsemann

Susin

Roesler

et al. 2011

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design

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“…The synthesis results are presented in Table 1 and some previous results of this work were presented in [29]. No timing restrictions were applied to the modules in the synthesis tool to generate these results.…”

Section: Synthesis Resultsmentioning

confidence: 99%

Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

Agostini¹,

Filho²,

Staehler³

et al. 2007

J. Braz. Comp. Soc.

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“…However, the stages are executed at different average processing time in video decoder implementation [6] . At most of time, the SBM between the inverse DCT and the intra/inter prediction stage is in case (2).…”

Section: Sbm Sizementioning

confidence: 99%

An improved asynchronous pipeline architecture for real-time video decoder implementation

2009

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Asynchronous pipeline structure is adopted for the real-time video decoder design because of its better performance when the stage processing times are irregular. However, the structure requires a lot of memories, the invaluable resource on chip, to buffer data and parameters between modules. To solve this problem, a specially designed switching buffer module is used between stages instead of traditional FIFO, and the module can also take some buffering function in each stage, which helps to reduce the utilization of memory. An H.264 decoder with the proposed structure was implemented. Compared to decoder without improved structure, the experimental decoder can save nearly 50% memory and 31% I/O operations between stages.

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FPGA Design of A H.264/AVC Main Profile Decoder for HDTV

Cited by 14 publications

References 9 publications

Efficient hardware solution for practical intra h.264/SVC video encoder implementation

Efficient hardware solution for practical intra h.264/SVC video encoder implementation

Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

An improved asynchronous pipeline architecture for real-time video decoder implementation

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