FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

Abstract

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

Asynchronous Early Output Dual-Bit Full Adder with Reduced Area

“…However, in comparison with Adder12, Adder15 achieves significant reduction in area by 18.8% while exhibiting a 2.3% increase in the latency. In the future, the utility of the proposed asynchronous RCA involving DBFAs and SBFAs for the effective realization of multi-operand additions [49] based on the bit-partitioning approach described in [50] could be considered since multi-operand addition operations are predominant in digital signal processing applications. Moreover, evaluating the cycle time of the various asynchronous RCAs discussed should be considered since the cycle time determines the rate (speed) at which fresh data can be input to an asynchronous circuit, where the cycle time is the sum of forward and reverse latencies.…”

Gecikme, alan, güç ve enerji açısından hibrit paralel toplayıcılar için karşılaştırmalı bir performans değerlendirmesi

“…Paralel önek ekleyicileri, ikili toplama problemine yüksek verimli bir çözüm sunar ve FPGA uygulaması için çok uygundur [8]. Mevcut CSLA mimarileri homojen ve heterojen tanımlanmış ve iki yeni hibrit CSLA topolojisi ortaya konmuştur: (i) seçme-alt bölüm-taşıma tabanlı taşıma ileriye dönük toplayıcı taşımak ve (ii) BEC mantığı da dahil olmak üzere seçim bölümü-taşıma tabanlı ileriye dönük toplayıcılar ve çeşitli CSLA yapılarının hız performansları vaka çalışmalarına göre analiz edilmiştir [9]. Han Carlson önek yapısı etkili önek yapısına sahip hibrit modüler paralel önek toplayıcının uygulanması analiz edilmektedir [10].…”

Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits

“…Ripple carry adders (RCA) [3] are area and power efficient, but with drawback of being slow. Carry-select adders (CSA) [2,[4][5][6][7][8][9][10] are one of the fastest adders among traditional adders, but they are not power and area efficient. Common Boolean Logic (CBL) [7] adders are area-power-delay efficient adders.…”