Four-phase micropipeline latch control circuits

Abstract

Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are levelsensitive, so two-to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.

472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device

“…Figure 1 (a) shows a micropipeline FIFO design target architecture. In the architecture, the most important circuit is a C-gate which has a role of synchronizing asynchronous signals between stages [6]. To implement the C-gates only with combinational gates and feedback signals in an FPGA, designers should care about the feedback signals which are automatically routed by commercial synchronous FPGA synthesis and P&R tools.…”

“…Particularly in [6], several handshake control circuits for the micropipelines have been proposed. Among the handshake control circuits, we choose "4-phase simple latch controller (SLC)" as our FIFO control circuits (shown in Figure 1 (b)) to show the possible speed limits of asynchronous circuits on an FPGA.…”

“…The other advanced handshake controllers need more gates for their decoupled operations, and it seems that the complex circuits of the advanced handshake controllers cause the significant increase in the cycle time of the FIFO. The advanced handshake control circuits can be employed for better performance when combinational circuits are inserted in between micropipeline stages [6].…”

Serialized Asynchronous Links for NoC

“…CLEAR (3) FLAG_S ( The asynchronous wire buffer is based on a simple four phase latch control circuit [15]. It essentially latches the data on the falling edge of REQIN.…”

Synthesis of asynchronous circuits using early data validity

“…The protocol presented here is applied to the synthesis of asynchronous circuits using handshake components. [10] provides designs for decoupled latch control circuits, but these controllers are compatible with the broad protocol, not with the early protocol. For the early protocol, as soon as the input is acknowledged, the data is allowed to change.…”