Abstract:In this paper, we design and analyze an asynchronous pipelined FIFO called a micropipeline with the awareness of "place & route" (P&R) on an FPGA device. We use a commercially available 65 nm Virtex-5 devices and design a high-speed implementation of the asynchronous four-phase micropipeline with considering its layout on the device. The layout of our design is modified manually to meet timing constraints and to accelerate the speed of circuits. The asynchronous FIFO implemented on the Virtex-5 device shows 452 MHz throughput and 648 ps per-stage latency at the simulation under the worst case operating condition and around 472 MHz throughput is observed at the actual measurement on a real working chip at room temperature.
Abstract. In this paper, we design and analyze two asynchronous circuits: 1) a simple micropipeline and 2) an asynchronous MIPS processor. We use a commercially available 65 nm Virtex-5 FPGA device for those two designs. The asynchronous FIFO implemented on the Virtex-5 device shows 452 MHz throughput at the simulation under the worst case operating condition. The micropipeline is extended to incorporate a conventional 5-stage pipelined MIPS datapath. Our asynchronous MIPS processor works successfully on the Virtex-5 FPGA device without a clock source, crystal oscillator, and 53.2 MHz throughput is measured.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.