Formulation of percolating thermal underfills using hierarchical self-assembly of micro- and nanoparticles by centrifugal forces and capillary bridging

Abstract

Thermal underfills are crucial to support integration density scaling of future integrated circuit packages. Therefore, a sequential process using hierarchical self-assembly of micro- and nanoparticles is proposed to achieve percolating thermal underfills with enhanced particle contacts. The three main process steps hereby are assembly of filler particles by centrifugation, formation of nanoparticle necks by capillary bridging, and the backfilling of the porous structure with an unfilled capillary adhesive. Numerical simulations predicting trajectories and distributions of micron-sized particles dispensed into a rotating disk are presented. The trajectories exhibit a strong dependence on the particle size; thus in the case of polydisperse filler particles nonuniform particle beds may result. An efficient centrifugal disk design with spiral-like guiding structures is experimentally validated. Defect-free, percolating particle beds in confined space with fill fractions of 46 vol-% to 66 vol-%, i.e., close to the theoretical limit, are also presented. The self-assembly of nanoparticles, forming enhanced thermal contacts between the percolating filler particles, is discussed. Two consecutive evaporation patterns during the capillary bridging process were identified: 1) dendritic network growth and 2) collapse of capillary bridges. The concave neck topology could only be achieved at temperatures below the boiling point. An optimal evaporation temperature of 60°C with respect to in-plane uniformity and neck shape was identified. Existing thermal gradients normal to the cavity surface resulted in strongly asymmetric neck formation in the cavity. Hence, uniform heating in an oven is the preferred method to initiate evaporation. Two types of bimodal dielectric necks are demonstrated. Polystyrene acts as the adhesive between thermally conductive alumina particles to form mechanically stable dielectric necks after an annealing step at 140°C. Interstitial and core-shell necks are presented. Finally, a benchmark study was performed to compare the effective thermal conductivity of the percolating thermal underfill with and without necks with state-of-the-art capillary underfills. A close to fivefold improvement could be obtained for diamond filler particles with silver necks (3.8 W/m-K).

Investigation of novel solder patterns for power delivery and heat removal support

“…Thermal underfills are under development to alleviate the effective thermal resistance of electrical joints between individual tiers in a chip stack [ 11,12]. The electrical joint is a major thermal bottleneck due to the low area fill fraction of approximately 21% in case of fully populated solder ball arrays (dummy solder balls are inserted to yield full population) [ 13,14].…”

In Situ Assembly in Confined Spaces of Coated Particle Scaffolds as Thermal Underfills with Extraordinary Thermal Conductivity

“…21 The top left inset in Figure 2b is the top view of the microparticle bed through the glass cover. Five liquids with varying surface tension values (σ lv =12−72 mN m −1 ) were used to analyze the movement behavior.…”

“…The total area is 7 cm × 7 cm and each pixel represents an area of 100 × 100 μm 2 . (c) Thermal conductivity of different underfills: (1) Commercial underfill based on silicon dioxide; (2) diamond microparticle with epoxy backfilling; (3) diamond microparticle with ethylenediamine liquid bridges; (4) diamond micro/nanoparticle composite with ethylenediamine coating.…”

Lattice Boltzmann modeling of heat conduction enhancement by colloidal nanoparticle deposition in microporous structures

“…Colloidal nanoparticle deposition on intended specific surfaces is also applied as ink-jet printing [5,6], or surface coating [7,8]. Recently, nanoparticle deposition has been used to enhance vertical heat conduction in innovative three-dimensional (3D) chip stacks to remove the heat generated in computer chips more efficiently [9][10][11]. In a 3D integrated chip stack, two or more layers of active electronic components are integrated vertically, as shown in Fig.…”

“…In the work of Refs. [9][10][11], percolating thermal structures [PTSs, Fig. 1(a)] and neck-based thermal structures [NTSs, Fig.…”