Formation of silicided, ultra-shallow junctions using low thermal budget processing

Osburn, C. M.

doi:10.1007/bf02655553

Cited by 73 publications

(4 citation statements)

References 85 publications

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“…Methods, such as projection gas immersion laser doping (PGILD) (Ishida 1992), plasma doping (PLAD) (Felch et al 1995) and very low-energy implants are being investig ultra-shallow junction formation (Sigmon & Weiner 1990). While junction silicides can further decrease incontact and series resistances, they are not compatible with ultra-shallow junctions because of metal penetration and associated leakage prob lems (Osburn 1990). Elevated source and drain junctions are therefore considered to form ultra-shallow junctions in silicon without encroachment into the channel, while maintaining an adequate 'buffer' for silicides and contacts.…”

Section: (E) Source and Drainmentioning

confidence: 99%

Addressing future analytical requirements of electronic materials

El-Kareh

1996

Phil. Trans. R. Soc. Lond. A

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The drive toward faster, denser, cheaper, lower power consuming and more reliable semiconductor products is predicted to continue relentlessly toward the end of the next decade, with a new generation introduced every three years. This is achieved by reducing horizontal and vertical device geometries, and by introducing more sophis ticated device structures. While these developments move at a fast pace, industries focus on rapid yield learning to reduce development costs. The key to fast process control and defect reduction is the implementation of efficient analytical and simu lation tools. After discussing trends in memory and logic, this paper focuses on key elements of CMOS structures and on characterization needs for successful develop ment of future technologies.

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Section: (E) Source and Drainmentioning

confidence: 99%

Addressing future analytical requirements of electronic materials

El-Kareh

1996

Phil. Trans. R. Soc. Lond. A

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“…Bipolar junction transistor contains two p-n junctions, JFET (junction fieldeffect transistor) has only one p-n junction and MOSFET contains a Schottky junction [4]. Junctionless transistor (JLFET) was introduced to replace the traditional junction transistor because of the challenges in scaling and complex thermal budget of the device [5]. Junctionless transistors can be described as variable resistors controlled by a gate electrode.…”

Section: Introductionmentioning

confidence: 99%

Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Sule¹,

Ramakrishnan

Alias

et al. 2020

IJEEI

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Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire fieldeffect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 10 19 cm -3 which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversionmode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance.

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“…The selfaligned silicide (SALICIDE) process has been widely considered to reduce the sheet resistance of both shallow junctions and polysilicon gates and to increase the contact area.24 However, having a silicided contact to shallow junctions provides added challenges associated with substrate consumption, interface roughness, and dopant redistribution. 5 In particular, the silicon substrate consumption can lead to unacceptable junction leakage if the silicide/silicon interface is too close to the depletion layer of the junction and to increased contact resistance when the suicide/silicon interface concentration is lowered since the highly doped region of the junction is consumed during silicidation.b Reducing the silicide thickness in accordaice with junction depth scaling, however, is limited by the high temperature stability of the thin suicide, difficul-ties in phase transformation from a high to a low resistivity phase, and the requirement of needing a thick suicide film for the interconnect line.…”

Section: Introductionmentioning

confidence: 99%

Parasitic Resistance Considerations of Using Elevated Source/Drain Technology for Deep Submicron Metal Oxide Semiconductor Field Effect Transistors

Bartholomew

Bellur

Srivastava

et al. 1998

J. Electrochem. Soc.

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Device drive current, parasitic resistance, and junction leakage current have been studied using silicided and nonsilicided deep submicron elevated source/drain (ESD) n-channel metal oxide semiconductor field effect transistors (NMOSFET5). This study illustrated the effects of doping profile in the elevated S/D region, junction depth in the substrate, and doping level in the source/drain extension. Compared to devices having nonelevated junctions with the same substrate doping profile, MOSFETs with a profile-doped elevated S/D, used to contact an ultrashallow junction formed before selective epitaxial growth, had higher drive currents and demonstrated the ability of the elevated junction to reduce the extrinsic resistance. Measurements of drive currents in ESD devices showed that (i) the lightly doped region at the bottom of a profile-doped elevated layer introduces additional extrinsic resistance, and (ii) the locally deeper junction beneath the epi facets extends laterally toward the channel and shortens the drain extension length, thereby reducing the intrinsic resistance. Silicided devices had higher drive current and reduced parasitic resistance when the silicide/silicon interfacial dopant concentrations remained high (>1 >< 1020/cm3) after silicidation. The lowest total parasitic resistance was achieved when the elevated S/D was used to give a small contact resistance to a shallow junction and a moderately doped drain extension was used to lower the resistance of the source/drain extension tab. * Electrochemical Society Active Member. * * Electrochemical Society Student Member. * * Electrochemical Society Fellow.

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Formation of silicided, ultra-shallow junctions using low thermal budget processing

Cited by 73 publications

References 85 publications

Addressing future analytical requirements of electronic materials

Addressing future analytical requirements of electronic materials

Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Parasitic Resistance Considerations of Using Elevated Source/Drain Technology for Deep Submicron Metal Oxide Semiconductor Field Effect Transistors

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