Formal equivalence checking between high-level and RTL hardware designs

Marquez, Carlos Ivan Castro; Strum, Marius; Chau, Wang Jiang

doi:10.1109/latw.2013.6562666

Cited by 12 publications

(2 citation statements)

References 7 publications

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“…Two examples of Equivalence Checking tools for hardware verification are EQUIPE and the framework from [43].…”

Section: Examples Of Equivalence Checking Toolsmentioning

confidence: 99%

“…This framework focuses on the equivalence checking between the electronic system level (ESL) and the RTL. To achieve this, according to [43], deep sequence comparison is performed, since there is no direct correlation between the internal states and architectures described in the ESL and in the RTL. This approach considers each input architecture as a finite state machine with data (FSMD).…”

Section: Castro Marquez's Frameworkmentioning

confidence: 99%

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A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

2018

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The high degree of miniaturization in the electronics industry has been, for several years, a driver to push embedded systems to different fields and applications. One example is safety-critical systems, where the compactness in the form factor helps to reduce the costs and allows for the implementation of new techniques. The automotive industry is a great example of a safety-critical area with a great rise in the adoption of microelectronics. With it came the creation of the ISO 26262 standard with the goal of guaranteeing a high level of dependability in the designs. Other areas in the safety-critical applications domain have similar standards. However, these standards are mostly guidelines to make sure that designs reach the desired dependability level without explicit instructions. In the end, the success of the design to fulfill the standard is the result of a thorough verification process. Naturally, the goal of any verification team dealing with such important designs is complete coverage as well as standards conformity, but as these are complex hardware, complete functional verification is a difficult task. From the several techniques that exist to verify hardware, where each has its pros and cons, we studied six well-established in academia and in industry. We can divide them into two categories: simulation, which needs extremely large amounts of time, and formal verification, which needs unrealistic amounts of resources. Therefore, we conclude that a hybrid approach offers the best balance between simulation (time) and formal verification (resources).

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“…Two examples of Equivalence Checking tools for hardware verification are EQUIPE and the framework from [43].…”

Section: Examples Of Equivalence Checking Toolsmentioning

confidence: 99%

Section: Castro Marquez's Frameworkmentioning

confidence: 99%

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

2018

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Enhancing active model learning with equivalence checking using simulation relations

Jeppu

Melham

Kroening

2022

Form Methods Syst Des

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We present a new active model-learning approach to generating abstractions of a system from its execution traces. Given a system and a set of observables to collect execution traces, the abstraction produced by the algorithm is guaranteed to admit all system traces over the set of observables. To achieve this, the approach uses a pluggable model-learning component that can generate a model from a given set of traces. Conditions that encode a certain completeness hypothesis, formulated based on simulation relations, are then extracted from the abstraction under construction and used to evaluate its degree of completeness. The extracted conditions are sufficient to prove model completeness but not necessary. If all conditions are true, the algorithm terminates, returning a system overapproximation. A condition falsification may not necessarily correspond to missing system behaviour in the abstraction. This is resolved by applying model checking to determine whether it corresponds to any concrete system trace. If so, the new concrete trace is used to iteratively learn new abstractions, until all extracted completeness conditions are true. To evaluate the approach, we reverse-engineer a set of publicly available Simulink Stateflow models from their C implementations. Our algorithm generates an equivalent model for 98% of the Stateflow models.

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An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL)

Strauch¹

2017

2017 Euromicro Conference on Digital System Design (DSD)

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Formal equivalence checking between high-level and RTL hardware designs

Cited by 12 publications

References 7 publications

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

Enhancing active model learning with equivalence checking using simulation relations

An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL)

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