A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

Grimm, Tomas; Lettnin, Djones; Hübner, Michael

doi:10.3390/electronics7060081

Cited by 34 publications

(19 citation statements)

References 48 publications

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“…In [37], Grimm et al studied six well-established techniques that exist to verify hardware and concluded that a hybrid approach offers the best balance between simulation (time) and formal verification (resources). Our proposal is such a hybrid verification approach for PLC programs, which attempts to combine testing or simulation and formal specification mining to directly provide evidence for verification.…”

Section: Related Workmentioning

confidence: 99%

A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

et al. 2020

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Programmable logic controllers (PLCs) are special embedded computers that are widely used in industrial control systems. To ensure the safety of industrial control systems, it is necessary to verify the correctness of PLCs. Formal verification is considered to be an effective method to verify whether a PLC program conforms to its specifications, but the expertise requirements and the complexity make it hard to be mastered and widely applied. In this paper, we present a specification-mining-based verification approach for IEC 61131-3 PLC programs. It only requires users to review specifications mined from the program behaviors instead of model checking for specified specifications, which can greatly improve the efficiency of safety verification and is much easier for control system engineers to use. Moreover, we implement a proof-of-concept tool named PLCInspector that supports directly mining LTL specifications and data invariants from PLC programs. Two examples and one real-life case study are presented to illustrate its practicability and efficiency. In addition, a comparison with the existing verification approaches for PLC programs is discussed.

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Section: Related Workmentioning

confidence: 99%

A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

et al. 2020

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“…Moreover, formal methods based techniques can be used to ensure the absence of faults in the system. According to a recent survey [35], most of the formal verification methods and tools are based on model checking and automated theorem provers that are restricted by wellknown state and memory explosion [37,38] problems. Formal verification using model checking is popular in industry [39,40] and well-studied domain by the research community [40][41][42]; however, the focus of this paper is on interactive theorem proving (ITP) [43][44][45] approach.…”

Section: Why Interactive Proof Assistant?mentioning

confidence: 99%

Formal Verification of Hardware Components in Critical Systems

Khan

Kamran

Naqvi

et al. 2020

Wireless Communications and Mobile Computing

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Hardware components, such as memory and arithmetic units, are integral part of every computer-controlled system, for example, Unmanned Aerial Vehicles (UAVs). The fundamental requirement of these hardware components is that they must behave as desired; otherwise, the whole system built upon them may fail. To determine whether or not a component is behaving adequately, the desired behaviour of the component is often specified in the Boolean algebra. Boolean algebra is one of the most widely used mathematical tools to analyse hardware components represented at gate level using Boolean functions. To ensure reliable computer-controlled system design, simulation and testing methods are commonly used to detect faults; however, such methods do not ensure absence of faults. In critical systems’ design, such as UAVs, the simulation-based techniques are often augmented with mathematical tools and techniques to prove stronger properties, for example, absence of faults, in the early stages of the system design. In this paper, we define a lightweight mathematical framework in computer-based theorem prover Coq for describing and reasoning about Boolean algebra and hardware components (logic circuits) modelled as Boolean functions. To demonstrate the usefulness of the framework, we (1) define and prove the correctness of principle of duality mechanically using a computer tool and all basic theorems of Boolean algebra, (2) formally define the algebraic manipulation (step-by-step procedure of proving functional equivalence of functions) used in Boolean function simplification, and (3) verify functional correctness and reliability properties of two hardware components. The major advantage of using mechanical theorem provers is that the correctness of all definitions and proofs can be checked mechanically using the type checker and proof checker facilities of the proof assistant Coq.

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“…As we will also demonstrate, additional faults can be found with FPV in designs that had already been verified by simulation [11,12]. Often it is only used for simple designs or control paths [13,8]. In [14], each design was first classified as suitable or not for FPV.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

A Functional Verification Methodology for Highly Parametrizable, Continuously Operating Safety-Critical FPGA Designs: Applied to the CERN RadiatiOn Monitoring Electronics (CROME)

Ceesay-Seitz

Boukabache

Perrin

2020

Lecture Notes in Computer Science

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Electronic systems that are related to human safety need to comply to strict international standards such as the IEC 61508. We present a functional verification methodology for highly parametrizable, continuously operating, safety-critical real-time systems implemented in FPGAs. It is compliant to IEC 61508 and extends it in several ways. We focus on independence between design and verification. Natural language properties and the functional coverage model build the connection between system safety requirements and verification results, providing forward and backward traceability. Our main verification method is Formal Property Verification (FPV), even for Safety Integrity Level 1 and 2. Further, we use constrained-random simulation in SystemVerilog with the Universal Verification Methodology and a design independent C reference model. When faults are discovered, the coverage model is extended to avoid regressions. Automation allows the reproduction of results and the reuse of verification code. We evaluate our methodology on a subset of the newly developed CERN RadiatiOn Monitoring Electronics (CROME). We present the challenges we faced and propose solutions. Although it is impossible to simulate the full design exhaustively, several formal properties have been fully proven. With FPV we found some safety-critical faults that would have been extremely hard to find in simulation.

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A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

Cited by 34 publications

References 48 publications

A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

Formal Verification of Hardware Components in Critical Systems

A Functional Verification Methodology for Highly Parametrizable, Continuously Operating Safety-Critical FPGA Designs: Applied to the CERN RadiatiOn Monitoring Electronics (CROME)

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