First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

Vandooren, A.; Franco, J.; Wu, Z.; Parvais, B.; Li, W.; Witters, L.; Walke, A.; Peng, Lan; Deshpande, V.; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Devriendt, K.; Teugels, Lieve; Heylen, N.; Vecchio, E.; Zheng, T.; Rosseel, Erik; Vanherle, W.; Hikavyy, Andriy; Mannaert, G.; Chan, B. T.; Ritzenthaler, R.; Mitard, J.; Ragnarsson, Lars‐Åke; Waldron, Niamh; Heyn, V. De; Demuynck, S.; Boemmels, J.; Mocuta, D.; Ryckaert, Julien; Collaert, N.

doi:10.1109/iedm.2018.8614654

Cited by 28 publications

(25 citation statements)

References 1 publication

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“…In advanced CMOS technology, in order to reduce the influence of the thermal budget on junction and channel quality, introducing the novel materials and processes are necessary in gate engineering. Therefore, the dipole formation in the gate stack is widely applied in the Replacement Metal Gate (RMG) process [168,169,170,171,172,173]. Usually, Lanthanum (La) and Aluminum (Al) are used to tune threshold voltage for NFET and PFET due to the different dipole polarity [168,169,170,171].…”

Section: Reliabilitymentioning

confidence: 99%

“…The CMOS integration flow together with a mechanism for PBTI improvement, which are shown as a band diagram in Figure 27b. For the reliability study, the impurity implantation in the HK&MG stack, such as “Nitrogen Implantation” in the work function metal layer [170] and the thickness tuning of an effective work function metal (EWF) can be investigated [170,171,172,173]. The advantage of such a study is to control the V T shift over a processed wafer, which provides very valuable information for chipmakers.…”

Section: Reliabilitymentioning

confidence: 99%

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Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Section: Reliabilitymentioning

confidence: 99%

Section: Reliabilitymentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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“…Although the continuous scaling down of complementary metal oxide semiconductor (CMOS) devices, following Moore's Law in the past several decades, has enabled an amazing increase in transistor count and, hence, in the integrated functionality on a single chip 1 , the information explosion in the forthcoming IoT era requires more functionalities even allowed beyond Moore's Law 2,3 . However, modern CMOS devices have already evolved to sub-10 nm technology nodes 4,5 , accompanied by many unwanted effects 6 , such as short-channel effects, variability, etc., which make it very difficult for them to undergo further scaling. It is still unclear at this stage whether CMOS community can manage to sustain Moore's Law for the next 10 years.…”

Section: Introductionmentioning

confidence: 99%

A mode-balanced reconfigurable logic gate built in a van der Waals strata

et al. 2021

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Two-dimensional (2D) semiconducting materials, in particular transition-metal dichalcogenides, have emerged as the preferred channel materials for sub-5 nm field-effect transistors (FETs). However, the lack of practical doping techniques for these materials poses a significant challenge to designing complementary logic gates containing both n- and p-type FETs. Although electrical tuning of the polarity of 2D-FETs can potentially circumvent this problem, such devices suffer from the lack of balanced n- and p-mode transistor performance, forming one of the most enigmatic challenges of the reconfigurable 2D-FET technology. Here we provide a solution to this dilemma by judicious use of van der Waals (vdW) materials consisting of conductors, dielectrics and semiconductors forming a 50 nm thin quantum engineered strata that can guarantee a purely vdW-type interlayer interaction, which faithfully preserves the mid-gap contact design and thereby achieves an intrinsically mode-balanced and fully reconfigurable all-2D logic gate. The intrinsically mode-balanced gate eliminates the need for transistor sizing and allows post-fabrication reconfigurability to the transistor operation mode, simultaneously allowing an ultra-compact footprint and increased circuit functionality, which can be potentially exploited to build more area-efficient and low-cost integrated electronics for the internet of things (IoT) paradigm.

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“…-DIMENSIONAL integrated circuit (3DIC) has been suggested as a breakthrough to increase device integration density in the situation where the scaling of gate pitch and device capacitance reaches a limit [2][3][4][5]. Fully-depleted (FD) silicon-on-insulator (SOI) field-effect-transistor (FET) is treated as a promising candidate in 3DIC because it has comparable performance (on/off current ratio) but is less expensive to fabricate than bulk Si fin-shaped FET (Si-FinFET) [6,7].…”

Section: Introductionmentioning

confidence: 99%

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Yun

Yoon

Jeong

et al. 2020

IEEE J. Electron Devices Soc.

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In this paper, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) Systemon-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors of 14-nm node FDSOI FETs. Also by using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications. These optimized structures were secured within the process range of conventional FDSOI FETs. Among the optimized parameters, drain-side spacer length (Lspd), source/drain junction gradient (Lsdj), and thickness of source/drain epi (Tsd) showed different behaviors for each application and thickness of buried oxide (Tbox) was maximal in optimization results. The detailed physical analysis was conducted to evaluate these parameters for each application. The neural network based optimization was powerful and efficient while saving time and cost in device design.

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First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

Cited by 28 publications

References 1 publication

Miniaturization of CMOS

Miniaturization of CMOS

A mode-balanced reconfigurable logic gate built in a van der Waals strata

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

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