Large-area graphene films are best synthesized via chemical vapour and/or solid deposition methods at elevated temperatures (~1,000 °C) on polycrystalline metal surfaces and later transferred onto other substrates for device applications. Here we report a new method for the synthesis of graphene films directly on sio 2 /si substrates, even plastics and glass at close to room temperature (25-160 °C). In contrast to other approaches, where graphene is deposited on top of a metal substrate, our method invokes diffusion of carbon through a diffusion couple made up of carbon-nickel/substrate to form graphene underneath the nickel film at the nickelsubstrate interface. The resulting graphene layers exhibit tunable structural and optoelectronic properties by nickel grain boundary engineering and show micrometre-sized grains on sio 2 surfaces and nanometre-sized grains on plastic and glass surfaces. The ability to synthesize graphene directly on non-conducting substrates at low temperatures opens up new possibilities for the fabrication of multiple nanoelectronic devices.

Highly efficient planar perovskite optoelectronic devices are realized by amine-based solvent treatment on compact TiO2 and by optimizing the morphology of the perovskite layers. Amine-based solvent treatment between the TiO2 and the perovskite layers enhances electron injection and extraction and reduces the recombination of photogenerated charges at the interface.

Copper-based interconnects employed in a wide range of integrated circuit (IC) products are fast approaching a dead-end due to their increasing resistivity and diminishing current carrying capacity with scaling, which severely degrades both performance and reliability. Here we demonstrate chemical vapor deposition-synthesized and intercalation-doped multilayer-graphene-nanoribbons (ML-GNRs) with better performance (more than 20% improvement in estimated delay per unit length), 25%/72% energy efficiency improvement at local/global level, and superior reliability w.r.t. Cu for the first time, for dimensions (down to 20 nm width and thickness of 12 nm) suitable for IC interconnects. This is achieved through a combination of GNR interconnect design optimization, high-quality ML-GNR synthesis with precisely controlled number of layers, and effective FeCl intercalation doping. We also demonstrate that our intercalation doping is stable at room temperature and that the doped ML-GNRs exhibit a unique width-dependent doping effect due to increasingly efficient FeCl diffusion in scaled ML-GNRs, thereby indicating that our doped ML-GNRs will outperform Cu even for sub-20 nm widths. Finally, reliability assessment conducted under accelerated stress conditions (temperature and current density) established that highly scaled intercalated ML-GNRs can carry over 2 × 10 A/cm of current densities, whereas Cu interconnects suffer from immediate breakdown under the same stress conditions and thereby addresses the key criterion of current carrying capacity necessary for an alternative interconnect material. Our comprehensive demonstration of highly reliable intercalation-doped ML-GNRs paves the way for graphene as the next-generation interconnect material for a variety of semiconductor technologies and applications.

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We show that acetone-derived graphene coating can effectively enhance the corrosion efficiency of copper (Cu) in a seawater environment (0.5-0.6 M (∼3.0-3.5%) sodium chloride). By applying a drop of acetone (∼20 μl cm(-2)) on Cu surfaces, rapid thermal annealing allows the facile and rapid synthesis of graphene films on Cu surfaces with a monolayer coverage of almost close to ∼100%. Under optimal growth conditions, acetone-derived graphene is found to have a relatively high crystallinity, comparable to common graphene grown by chemical vapor deposition. The resulting graphene-coated Cu surface exhibits 37.5 times higher corrosion resistance as compared to that of mechanically polished Cu. Further, investigation on the role of graphene coating on Cu surfaces suggests that the outstanding corrosion inhibition efficiency (IE) of 97.4% is obtained by protecting the underlying Cu against the penetration of both dissolved oxygen and chlorine ions, thanks to the closely spaced atomic structure of the graphene sheets. The increase of graphene coating thickness results in the enhancement of the overall corrosion IE up to ∼99%, which can be attributed to the effective blocking of the ionic diffusion process via grain boundaries. Overall, our results suggest that the acetone-derived graphene film can effectively serve as a corrosion-inhibiting coating in the seawater level and that it may have a promising role to play for potential offshore coating.

. This will require a tremendous number of miniaturized wireless connections that are driven by radio frequency (RF) integrated circuits (RF-ICs) that demand scalability, flexibility, high performance and ease of integration. Moreover, the market value of radio frequency identification (RF-ID), which employs electromagnetic fields to automatically identify and track tags attached to objects, is expected to rise to US$18.68 billion by 2026 4 . Planar on-chip metal inductors (Fig. 1a) are essential passive devices in RF-ICs and can occupy up to 50% of the chip area. They also contribute a major part of the form factor of RF-IDs (see Supplementary Section 1). However, unlike the continuous scaling of transistors and interconnects in IC technology, which was achieved with an increase in performance, progress toward miniaturization of on-chip inductors has remained elusive, mainly due to the fact that large inductor areas, dictated by fundamental electromagnetics, are required to deliver desirable inductance values and performance targets ( Fig. 1b; see also Supplementary Section 2).To achieve continuous size scaling while fulfilling the inductance and performance requirements, improvement in the inductance density is essential, which is defined by inductance per unit area = total inductance (L total ) / inductor area, where L total is the sum of the magnetic inductance (L M ) and the kinetic inductance (L K ) (Fig. 1a). Magnetic inductance is the property of an electrical conductor by which a change in current through it, causing a change in the magnetic flux, induces an electromotive force in both the conductor itself (self-inductance) and in any nearby conductors (mutual inductance) that opposes the change. Kinetic inductance is the manifestation of the inertial mass of mobile charge carriers in alternating electric fields as an equivalent series inductance. L K arises naturally as the inductive impedance per unit length of the conductor in the Drude model for a.c. electrical conductivity. Hence, the magnetic inductance is determined by the geometrical/ structural design of the inductor, while kinetic inductance is purely a material property (see Supplementary Section 3 for more details). Therefore, structural design and materials innovation, that determine L M and L K , respectively, are two simultaneous ways to improve the inductance density. As shown in the example in Fig. 1b, a comparable L K (if it exists) with respect to L M can significantly improve both the inductance and the quality factor (Q-factor, or Q, the ratio of the inductive reactance to the resistance of an inductor at a given frequency, which is a measure of its efficiency). However, because in conventional metals L K is negligibly small (because of relatively weak carrier inertia) compared to L M , almost all studies in the past few decades have been focused on structural improvements to make full use of the magnetic field, such as layout optimization 5 , micro-electromechanical-system fabrication 6,7 , three-dimensional self-rolled-up 8 and ve...

Today, state-of-the-art III-Ns technology has been focused on the growth of c-plane nitrides by metal-organic chemical vapor deposition (MOCVD) using a conventional two-step growth process. Here we show that the use of graphene as a coating layer allows the one-step growth of heteroepitaxial GaN films on sapphire in a MOCVD reactor, simplifying the GaN growth process. It is found that the graphene coating improves the wetting between GaN and sapphire, and, with as little as ~0.6 nm of graphene coating, the overgrown GaN layer on sapphire becomes continuous and flat. With increasing thickness of the graphene coating, the structural and optical properties of one-step grown GaN films gradually transition towards those of GaN films grown by a conventional two-step growth method. The InGaN/GaN multiple quantum well structure grown on a GaN/graphene/sapphire heterosystem shows a high internal quantum efficiency, allowing the use of one-step grown GaN films as 'pseudo-substrates' in optoelectronic devices. The introduction of graphene as a coating layer provides an atomic playground for metal adatoms and simplifies the III-Ns growth process, making it potentially very useful as a means to grow other heteroepitaxial films on arbitrary substrates with lattice and thermal mismatch.

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