Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Yun, Hyeok; Yoon, Jun-Sik; Jeong, Jinsu; Lee, Seung-hwan; Choi, Hyun‐Chul; Baek, Rock‐Hyun

doi:10.1109/jeds.2020.3022367

Cited by 9 publications

(6 citation statements)

References 17 publications

(19 reference statements)

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“…There are regression models that predict the threshold voltage or SS based on the structural information regarding the device [33][34][35]. However, they could not be applied to our model for three reasons.…”

Section: (B))mentioning

confidence: 99%

Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors

et al. 2023

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In this study, we propose a deep neural network (DNN) model that extracts the subgap states in the channel layer of oxide thin-film transistors. We have developed a framework that includes creating a model training set, preprocessing the data, optimizing the model structure, decoding from density-of-state (DOS) parameters to current-voltage (I-V) characteristics, and evaluating the model performance and accuracy of curve fitting. We investigate in detail the effect of data preprocessing methods and model structure on the performance of the model. The primary finding is that the input data type and the last hidden layer significantly affects the performance of the regression model. Using double-type input data composed of several voltages and linear current values is more advantageous than using log-scale current. Moreover, the number of nodes in the last hidden layer of a regression model with multiple output nodes should be large enough to avoid interference between the output values. The proposed model outputs five DOS parameters, and the resulting parameters are decoded to an I-V curve through interpolation based on the nearest 32 data from the given dataset. We evaluate the model performance using the threshold voltage and on-current difference between a target curve and the decoded curve. The proposed model calibrates 97.1% of the 14,400 curves within the threshold voltage difference of 0.2V and on-current error of 5%. Hence, the proposed model is verified to effectively extract DOS parameters with high accuracy based on the current characteristics of oxide thin-film transistors. We expect to improve the efficiency of defect analysis by replacing the iterative manual technology computer aided design (TCAD) curve fitting with an automatic DNN model.

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Section: (B))mentioning

confidence: 99%

Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors

et al. 2023

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“…ML predicts the devices having better performance than those in the datasets. Errors are smaller when predicting RC delay of n-type NWFETs for HP application because the output ratio (outputmax/outputmin) from the datasets is small [16]. This factor means the difference of the output parameters used for ML because the output parameters are logged on the RC delay and the RF FoM.…”

Section: B Performance Optimization Using ML Approachmentioning

confidence: 99%

“…However, since the fabrication flows are different from conventional horizontal FETs, it is needed to optimize the device structure to boost its performance and finally to provide the device guideline. Therefore, in this work, we optimize digital and analog performances of vertical NWFETs using fully-calibrated TCAD and machine learning (ML) technique which has been adopted for the optimization of silicon-on-insulator FETs [15], [16]. DC/AC characteristics of vertical NWFETs in terms of geometry and doping have been studied in detail.…”

Section: Introductionmentioning

confidence: 99%

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

et al. 2021

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Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital and analog performances using fully-calibrated TCAD and machine learning (ML) technique. Digital performance is quantified by RC delay (CggVdd/Ion, where Cgg is gate capacitance, Vdd is operation voltage, and Ion is on-state current) at the fixed off-state currents, and analog performance is quantified by the product of cutoff frequency (Ft) and transconductance efficiency (Gm/Ids). ML accurately predicted the geometry and doping parameters suggesting the best device performances. All the optimized NWFETs have larger drain diameters but smaller source diameters at the minimum of gate lengths, gate oxide thicknesses, drain junction gradients, and source/drain spacer lengths. Small source diameters are needed to tightly control the energy barrier to reduce the short-channel effects, whereas large drain diameters increase current drivability than Cgg. Small drain junction gradients increase the lateral electric field from source to drain, which increases the carrier velocity. Longer spacer lengths decrease both Ion and Cgg, but the Ion degradation is critical. These device characteristics validate the optimization results from ML, and ML-based optimization is fast and effective to maximize both digital and analog performances.

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“…Machine learning (ML) in this study can help in determining the optimal values exactly and rapidly. ML has recently been used to predict and optimize nanoscale transistors [16], [17], [18]. An artificial neural network (ANN) modeled the relationship between the trap distributions as input parameters and the absolute values of the threshold voltage shift (| V th |) as the output parameters.…”

Section: Introductionmentioning

confidence: 99%

Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning

et al. 2023

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A machine learning (ML) method was used to optimize the trap distribution of the charge trap nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics, which are tradeoffs in 3-D NAND flash memories. Using an artificial neural network (ANN), we modeled the relationship between trap distributions and P/R characteristics. The ANN was trained using a large experimentallycalibrated technology computer-aided design (TCAD) simulation dataset. The gradient descent method was adapted to optimize the trap distribution, achieving the best P/R characteristics based on the welltrained ANN. Eventually, we found the best trap profile distributed in both space and energy. In particular, the energetic trap distribution had a larger impact on the P/R characteristics than that of the spatial trap distribution. Furthermore, in terms of the P/R characteristics, it was generally preferable to increase all inputs of the energetic trap distribution. However, the acceptor-like trap energy level (E TA ) and its standard deviation (σ EA ) caused a tradeoff between P/R characteristics; therefore, ML was used to determine their optimal points. The proposed ML method allows the optimization of trap distribution to obtain the best P/R characteristics rapidly and quantitatively. Our findings could be used as a guideline for determining the physical properties of CTN in 3-D NAND flash cells.

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Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

Cited by 9 publications

References 17 publications

Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors

Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning

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