FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys

Gaidai, Oleg; Liu, Z.; Niimi, Hiroaki; Mochizuki, Seibu; Fronheiser, Jody; Miao, Xin; Li, J.; Demarest, J.; Zhang, Chen; Niu, C.; Liu, B.; Petrescu, A.; Adusumilli, Praneet; Yang, Jong-Chul; Jagannathan, H.; Bu, H.; Yamashita, Takako

doi:10.1109/iedm.2016.7838437

Cited by 35 publications

(17 citation statements)

References 5 publications

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“…And then, we use R c = ρ c /L conact × 2, where L contact is the contact length, and the factor 2 arises because R c includes effects of both source and drain. In this discussion, we assume L contact = 8 nm In the Appendix, as a supplementary approach to discuss the effect of material-dependent ρ c , we provide another CV 2 vs. CV/I plot using R SD estimated from the best experimental ρ c reported in literatures for each material [55], [122], [134], [135] (also see Figs. 18-20).…”

Section: Discussion: Effects Of Contact Resistivitymentioning

confidence: 99%

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Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

Kim

Avci

Young

2020

IEEE J. Electron Devices Soc.

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Comprehensive channel material benchmarking for n-and pMOS are performed considering effects of quantum transport and carrier scattering. Various channel material options (Si, InAs, In 0.7 Ga 0.3 As, In 0.53 Ga 0.47 As, GaAs, and Ge for nMOS, Si and Ge for pMOS) are covered using hybrid simulation of quantum ballistic transport and semi-classical Monte Carlo. Current-voltage characteristics and performance metrics such as the capacitance and effective drive current (I eff) are explored considering device parasitic components. For low power operation, III-V nMOS may deliver good performance while Ge n-and pMOS with different source/drain tip designs may give performance advantage over Si from low power to high performance operations. CMOS benchmarking results for I eff , capacitance, and switching energy vs. delay (for gate capacitance loading vs. interconnect wire capacitance loading) are also presented for various homogeneous and hybrid combinations of n-and pMOS (Si CMOS, III-V hybrid CMOS, Ge hybrid CMOS, and Ge CMOS). Finally, sensitivity analysis is performed for I eff on the parasitic resistance (R SD) and contact resistivity (ρ c). Novel channel materials may relax the R SD and ρ c requirements to match the I eff performance of Si reference. Comprehensive literature reviews of experimental ρ c 's of novel materials are also presented to discuss the effect of material-dependent R SD .

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Section: Discussion: Effects Of Contact Resistivitymentioning

confidence: 99%

“…Fig. 24(a)-(c) shows simulation results for CV 2 vs. CV/I and relative comparison with Si CMOS using R SD estimated from the best experimental ρ c reported in literatures for each material, n-and p-Si [134], n-In 0.53 Ga 0.47 As [55] (see Fig. 18), n-Ge [122] (Fig.…”

Section: Discussionmentioning

confidence: 99%

Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

Kim

Avci

Young

2020

IEEE J. Electron Devices Soc.

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“…Recent developments in doping technology have exceeded 10 21 cm [30], and such heavy S/D doping could also enhance the drive current. Nevertheless, contact resistance remains one of the greatest challenges for 5 nm technology.…”

Section: Appl Sci 2018 8 54 8 Of 14mentioning

confidence: 99%

Correlation between the Golden Ratio and Nanowire Transistor Performance

Al-Ameri

2018

Applied Sciences

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An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi). In turn, a simulation was conducted regarding ultra-scaled n-type Si (NWT) with respect to the 5-nm complementary metal-oxide-semiconductor (CMOS) application. The results reveal that the amount of mobile charge in the channel and intrinsic speed of the device are determined by the device geometry and could also be correlated to the golden ratio (Phi). This paper highlights the issue that the optimization of NWT geometry could reduce the impact of the main sources of statistical variability on the Figure of Merit (FoM) of devices. In the context of industrial early successes in fabricating vertically stacked NWT, ensemble Monte Carlo (MC) simulations with quantum correction are used to accurately predict the drive current. This occurs alongside a consideration of the degree to which the carrier transport in the vertically stacked lateral NWTs are complex.

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“…1,[6][7][8][9][10][11][12] Moreover, recent requirement of ultra-low contact resistivity pushes the employment of the high doping processes such as ISPD silicon epitaxial process by the phosphorous concentration at the source/drain up to 4 × 10 21 cm −3 . [13][14][15] This reduces the metal-semiconductor Schottky barrier width, which in turn increases the carrier tunneling and reduces the contact resistivity. 16) Despite the development on the growth of ISPD epitaxial silicon layer, certain challenges must first be overcome before the utilization in 3D devices.…”

mentioning

confidence: 99%

Defect reduction and dopant activation of in situ phosphorus-doped silicon on a (111) silicon substrate using nanosecond laser annealing

Kim

2021

Appl. Phys. Express

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In situ phosphorus-doped silicon (ISPD) has been actively investigated as a source/drain material. However, defect formation during the epitaxial growth of ISPD layers in 3D structures deteriorate the device performance. In this study, we investigate the elimination of inherent defects in ISPD layers using nanosecond laser annealing (NLA). High-density twin- and stacking-fault defects in the ISPD layers cause strain relaxation and dopant deactivation. The NLA process dramatically reduces or eliminates the defects, consequently generating the strain and electrically activating the incorporated phosphorous. The ISPD epitaxial growth and subsequent NLA processes will be robust methods for the fabrication of advanced 3D devices.

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FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys

Cited by 35 publications

References 5 publications

Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

Correlation between the Golden Ratio and Nanowire Transistor Performance

Defect reduction and dopant activation of in situ phosphorus-doped silicon on a (111) silicon substrate using nanosecond laser annealing

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