Fine pitch chip interconnection technology for 3D integration

Hwang, Ji-Hwan; Kim, Jongyeon.; Kwon, Woocheol; Kang, Un-Byoung; Cho, Tae-Je; Kang, Sayoon

doi:10.1109/ectc.2010.5490821

Cited by 46 publications

(13 citation statements)

References 6 publications

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“…Thin chip stacking with vertical interconnection by Cu TSV combination with Cu/Sn micro-joint is an attractive option for 3D integration [1][2][3][4]. However, this approach is usually limited by C2C or C2W bonding followed by underfill filling for reliability enhancement.…”

Section: Introductionmentioning

confidence: 99%

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Hsiao

Chang

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5µm TSV, 10µm microbump, 20µm pitch, 40µm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications. IntroductionThin chip stacking with vertical interconnection by Cu TSV combination with Cu/Sn micro-joint is an attractive option for 3D integration [1][2][3][4]. However, this approach is usually limited by C2C or C2W bonding followed by underfill filling for reliability enhancement. The schemes usually need thin wafer handling technique with carrier temporary bonding to handle the thin wafer for backside processes, and followed by carrier de-bonding and dicing into dies for chip level assembly. The high crack risk exists on thin wafer de-bonding and thin chip assembly, and the underfill filling becomes more and more challenging as the gap between stacked chips becomes smaller and smaller. Considering the application in future, it will be more beneficial to develop a carrier-less 3D integration platform with simplified process flow at wafer-level to increase the yield, through-put and lower the cost.Cu-Cu thermo-compression bond is a popular approach for wafer-level bonding scheme because it provides excellent electrical performance and bonding strength. However, it requires high bonding force and temperature, and un-bonded area with air gap may result in reliability issues. Many hybrid bonding schemes by Cu/adhesive or Cu/oxide have been carried out to solve the reliability issues, but the bonding or annealing temperature higher than 300°C are still required to perform the bonding integrity [5][6][7][8]. The high temperature may result in high thermo-stress and possible damages to the low thermal budget and sensitive devices.To provide a carrier-less, simplified flow, low temperature, and high reliable solution, a wafer-level 3D

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Section: Introductionmentioning

confidence: 99%

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Hsiao

Chang

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…Due to tremendous effort of many research organizations and industries, state-of-art TSV forming and copper via filling can be successfully developed. As TSV vertical interconnection methods, Cu pillar/Sn-Ag bump structure is being widely investigated for 3D TSV chip stacking [2][3][4][5][6][7][8]. Recently, 40 lm pitch TSV-chip stacking is being applied in real products in IBM, Xillinx, Samsung, etc., however, there are two major problems in Cu pillar/ Sn-Ag bonding.…”

Section: Introductionmentioning

confidence: 99%

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40μm pitch Cu-pillar/Sn–Ag bump interconnection

Shin

Kim

Choi

et al. 2015

Microelectronics Reliability

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“…Three-dimensional integration circuit (3DIC) has become a very promising technology in the semiconductor industry, recently [1][2][3][4][5]. By introducing the structure of through silicon via (TSV) inside the die, vertically multiple-die stack would be practicable.…”

Section: Introductionmentioning

confidence: 99%

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections

Huang

Zhan

Juang

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Fine pitch chip interconnection technology for 3D integration

Cited by 46 publications

References 6 publications

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40μm pitch Cu-pillar/Sn–Ag bump interconnection

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections

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Fine pitch chip interconnection technology for 3D integration

Cited by 46 publications

References 6 publications

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40μm pitch Cu-pillar/Sn–Ag bump interconnection

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60&#x0446;m-pitch solder micro bump interconnections

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Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections