Finding good counter-examples to aid design verification

Fey, Görschwin; Dreschler, R.

doi:10.1109/memcod.2003.1210088

Cited by 14 publications

(16 citation statements)

References 3 publications

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“…The approach in [3] heuristically chooses fault candidates that are fixes to a set of counterexamples. But, no guarantee is given that one of the counterexamples contains more information than another one.…”

Section: Limitationsmentioning

confidence: 99%

“…Note that, using a heuristic technique for counterexample generation, e.g. [3], does not guarantee to increase the accuracy. Figure 5 shows detailed results for a few example runs.…”

Section: A Accuracymentioning

confidence: 99%

“…But obviously, using all counterexamples is not feasible in practice. Instead, a subset has to be chosen, where choosing the best subset is NPcomplete [3]. Therefore the counterexamples are typically chosen randomly and the fault candidates are not guaranteed to be complete.…”

Section: Introductionmentioning

confidence: 99%

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Increasing the accuracy of SAT-based debugging

Sülflow

Fey

Braunstein

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. In particular, debugging based on Boolean Satisfiability (SAT) has been shown to be quite efficient. Given some error traces, the algorithm returns fault candidates. But using random error traces cannot ensure that a fault candidate is sufficient to explain all erroneous behaviors.Our approach provides a more accurate diagnosis by iterating the generation of counterexamples and debugging. This increases the accuracy of the debugging result and yields more valuable counterexamples. As a consequence less time consuming manual iterations between verification and debugging are required -thus the debugging productivity increases.

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Section: Limitationsmentioning

confidence: 99%

“…Note that, using a heuristic technique for counterexample generation, e.g. [3], does not guarantee to increase the accuracy. Figure 5 shows detailed results for a few example runs.…”

Section: A Accuracymentioning

confidence: 99%

See 1 more Smart Citation

Increasing the accuracy of SAT-based debugging

Sülflow

Fey

Braunstein

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

Self Cite

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show abstract

“…G.Fey [11] analysis the counterexample of equivalence checking, and generate multiple similar counterexample, then locate the actual error by analysis commonness of these counterexample.…”

Section: Error Locatingmentioning

confidence: 99%

Localizing Errors in Counterexample with Iteratively Witness Searching

Shen

Qin

2004

Automated Technology for Verification and Analysis

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Abstract. We propose a novel approach to locate errors in complex counterexample of safety property. Our approach measures the distance between two state transition traces with difference of their control flow. With respect to this distance metrics, our approach search for a witness as near as possible to the counterexample. Then we can obtain the set of control flow predicates with difference assignment in witness and counterexample. Run this witness-searching algorithm iteratively, we can then obtain a predicate list with priority. A predicate with higher priority means that this predicate is more likely the actual error. Experiment result shows that our approach is highly accurate.

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“…This has been considered in the basic approach already [8]. The selection of counterexamples that improve the accuracy can be automated by using a heuristic [14] or a given specification [15], [16]. In particular for sequential circuits the resolution in the time domain can be further improved by differentiating at what time frames a correction at a certain fault candidate (e.g., a module or a gate) is required and in which other time frames no modification is required [17].…”

Section: Introductionmentioning

confidence: 99%

Towards Unifying Localization and Explanation for Automated Debugging

Fey

Sülflow

Drechsler

2010

2010 11th International Workshop on Microprocessor Test and Verification

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Abstract-Today, there exist powerful algorithms for automated debugging. Some of the debugging algorithms focus on fault localization while others try to explain the faulty behavior by providing, e.g., correct traces that are similar to a failure trace. SAT-based debugging locates faults, but does not explain the faulty behavior, e.g., some temporal properties of fault candidates are not fully explored.In this work, we study the resolution of SAT-based debugging with respect to its capability to locate faults and to explain faults. A strategy is presented that increases the diagnostic resolution of SAT-based debugging by combining fault localization and fault explanation in one algorithm. The experimental results confirm the strength of the approach and give directions for further research.

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Finding good counter-examples to aid design verification

Cited by 14 publications

References 3 publications

Increasing the accuracy of SAT-based debugging

Increasing the accuracy of SAT-based debugging

Localizing Errors in Counterexample with Iteratively Witness Searching

Towards Unifying Localization and Explanation for Automated Debugging

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