Ferroelectric Nonvolatile Nanowire Memory Circuit Using a Single ZnO Nanowire and Copolymer Top Layer

Abstract

Nanowire-based fi eld-effect transistors (FETs) and diodes have been continuously studied along with a great variety of semiconductor nanowires (NWs), including Si, Ge, SiGe, GaN, InP, and ZnO. [1][2][3][4][5][6][7][8] Among all the NW materials, ZnO appears to have relatively good metal electrode-semiconductor contact, which improves the device fabrication yield. [7][8][9][10][11][12][13][14][15][16][17] Therefore, using a long ZnO NW it may be possible to realize one-dimensional (1D) NW electronics, which may contain a FET, [ 7 , 10-14 ] diode, [ 8 , 14,15 ] resistor, memory, [ 16 , 17 ] and other components in a single NW, even though such 1D electronics have rarely been demonstrated so far. [ 8 , 13,14 ] Since nonvolatile memory is an important component for device electronics in general, quite a few studies on memory components in NW dimensions have been reported. However, most attempts were property characterization studies of nanomaterials and prototype devices in general, [16][17][18][19][20][21][22][23][24][25][26] and indeed substantial efforts to incorporate the memory devices into 1D circuit electronics are diffi cult to fi nd. [ 27 ] In particular, ferroelectric memory NW FETs [ 16 , 21 , 22 ] are very rare while charge injection memory-type devices [ 17-20 , 27 ] are relatively common. In the work reported here, we have fabricated a top-gate ferroelectric memory FET from a ZnO NW and the organic copolymer poly(vinylidenefl uoride-trifl uoroethylene) [P(VDF-TrFE)], aiming at a 1D nonvolatile memory circuit in NW-based electronics. Since our single ZnO NW was long enough to have an extra region for an electrical resistor beyond the main region for the top-gate ferroelectric FET (FeFET) channel, we were able to simply realize a ferroelectric memory inverter circuit using one single NW. Our success is closely related to how we patterned the top-gate metal on the organic ferroelectric polymer, which was not easy to perform by photolithography for a channel just a few micrometers long contacting P(VDF-TrFE). Our FeFET with 150 nm-thin ZnO NW channel clearly displayed a memory hysteresis window, which is as large as ca. 20 V, along with an average linear mobility of ca. 67 cm 2 V − 1 s − 1 . This memory window was confi rmed in voltage hysteresis characteristics (VHCs) of our memory circuit, which consists of the ZnO NW-based FeFET and serially connected NW www.advmat.de www.MaterialsViews.com wileyonlinelibrary.com

Side‐Gated In2O3 Nanowire Ferroelectric FETs for High‐Performance Nonvolatile Memory Applications

“…Although the gate pulses used in the dynamic characteristic test are much shorter than those used in stability and endurance tests, a dynamic retention ratio of about 10 5 is still observed under V ds of 0.1 V. Here we also studied the current dynamics of devices with the same D and different W (see Figure S6 in the Supporting Information), the result is in good agreement with our discussion about the impact of different gate sizes. All these results demonstrate an excellent nonvolatility memory behavior of our side‐gated FeFETs, by reference to ferroelectric memory with top‐gated or back‐gated structure in previous works 5, 13, 17, 28, 36…”

“…It is also noted that our side‐gated devices exhibit excellent performances at room temperature and in ambient air. The leakage current, on/off current ratio, and subthreshold slope ( SS ) all present superior values as compared with those of NW‐based FeFETs reported previously 5, 12, 13, 17, 27. Also, the memory hysteresis characteristics can be effectively controlled by adjusting the side‐gated geometrical parameters.…”

“…In recent years, ferroelectric field‐effect transistors (FeFETs) have been widely studied as an important type of memory due to their remarkable characteristics of nonvolatility, low power consumption, fast operation speed, and nondestructive memory operation 1, 2, 3, 4, 5. Until now, among all promising ferroelectric materials explored in FeFETs, organic ferroelectric polymers contain the exceptional advantages of light weight, mechanical flexibility, and low‐temperature solution‐base processing, which are ideal for the large area technological utilizations 6, 7, 8, 9, 10.…”

“…Importantly, the stable remnant polarization of the P(VDF‐TrFE) dielectric layer can enable an ultrahigh local electrostatic field in the semiconductor channel, which is much larger than that produced by the gate bias in traditional field‐effect transistors;15, 16 in this case, the transport properties of the channel can be effectively modulated under a relatively low gate bias or even stayed in depletion or accumulation state after the gate bias is removed. However, since P(VDF‐TrFE) is highly soluble in common organic solvents, it is cumbersome to fabricate electronic devices with P(VDF‐TrFE) in the top‐gated configuration with short channel lengths (i.e., sub‐μm) via conventional ultraviolet or electron‐beam lithography (EBL) techniques 5, 17. In addition, if the P(VDF‐TrFE) film is irradiated by the electron‐beam, the ferroelectric properties of P(VDF‐TrFE) would be degenerated into relaxor (see Figure S1 in the Supporting Information) 18.…”

“…The short‐range V gs sweep after the program and erase pulses can also confirm the memory effect of our inverter circuit (see Figure S7 in the Supporting Information). Furthermore, the distinguishability of disparate states in the memory circuit can be estimated by the memory output ratio,5 which is defined as ( V out,Pro − V out,Er )/ V DD × 100%. With resistors (R 1 +R 2 ), a memory output ratio of ≈85% is achieved in the inverter.…”