Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages

Padilla, Alvaro; Yeung, Chun Wing; Shin, Changhwan; Hu, Chenming; Liu, Tsu‐Jae King

doi:10.1109/iedm.2008.4796643

Cited by 97 publications

(73 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…When decreasing V DS (i.e., the lateral electric field), the impact ionization rate decreases, and the SS gradually degrades to 61 mV/dec at V DS =1V. Compared to counterparts with significant hysteresis [5][8], double sweep confirms the negligible hysteresis in the characteristics of the proposed device. Fig.…”

Section: Resultsmentioning

confidence: 66%

“…Impact-ionization MOS (IMOS) achieves sub-5 mV/dec SS based on avalanche breakdown [4], though requiring high V DS and suffering from reliability issues. Based on an asymmetric structure similar to TFET and IMOS, feedback FET realizes steep SS with large hysteresis due to the charge trapping [5]. Recently, positive feedback based on weak impact ionization was proposed to achieve super-steep SS on UTBOX FDSOI substrate [6].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current

Zhang

Marchi

Gaillardon

et al. 2014

2014 IEEE International Electron Devices Meeting

View full text Add to dashboard Cite

show abstract

Section: Resultsmentioning

confidence: 66%

Section: Introductionmentioning

confidence: 99%

A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current

Zhang

Marchi

Gaillardon

et al. 2014

2014 IEEE International Electron Devices Meeting

View full text Add to dashboard Cite

show abstract

“…4 In recent years, numerous studies have examined various approaches to overcome this limit of 60 mV/dec. [4][5][6][7][8] Of these, two approaches are considered the most promising. One is the use of tunneling FET, an ambipolar device in principle that exhibits a p-type behavior with dominant hole conduction and an n-type behavior with dominant electron conduction.…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Wang

Chen

et al. 2017

npj 2D Mater Appl

View full text Add to dashboard Cite

Conventional field-effect transistors (FETs) are not expected to satisfy the requirements of future large integrated nanoelectronic circuits because of these circuits' ultra-high power dissipation and because the conventional FETs cannot overcome the subthreshold swing (SS) limit of 60 mV/decade. In this work, the ordinary oxide of the FET is replaced only by a ferroelectric (Fe) polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)). Additionally, we employ a two-dimensional (2D) semiconductor, such as MoS 2 and MoSe 2 , as the channel. This 2D Fe-FET achieves an ultralow SS of 24.2 mV/dec over four orders of magnitude in drain current at room temperature; this sub-60 mV/dec switching is derived from the Fe negative capacitance (NC) effect during the polarization of ferroelectric domain switching. Such 2D NC-FETs, realized by integrating of 2D semiconductors and organic ferroelectrics, provide a new approach to satisfy the requirements of next-generation low-energy-consumption integrated nanoelectronic circuits as well as the requirements of future flexible electronics.

show abstract

“…Feedback TFETs [38] and Z2-FET [39], with a forward biased PIN diode, have shown experimentally very small S (a few mV/dec) together with good I on , however for biases larger than 0.5 V.…”

Section: Tunnel Fetsmentioning

confidence: 98%

Ultralow-Power Device Operation

Balestra

2015

Nanoscale Materials and Devices for Electronics, Photonics and Solar Energy

View full text Add to dashboard Cite

The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition. We are facing today dramatic challenges dealing with the limits of energy consumption and heat removal, inducing fundamental tradeoffs for the future ICs. A substantial reduction of the static and dynamic power is strongly needed for the development of future high-performance/ultralow-power terascale integration and autonomous nanosystems.This chapter of the tutorial book addresses the main trends, challenges, limits, and possible solutions for strongly reducing the energy per binary switching. Several paths are possible, the most promising one being the reduction of static and dynamic energy consumption using conventional logic with a reduction in the stored energy and therefore a decrease of device capacitance C (device integration) and applied bias V, together with a decrease of leakage currents of nanodevices.The best potential solutions are ultrathin-film SOI (silicon-on-insulator) and multi-gate devices, nanowires, and small-slope switches (tunnel FETs, ferroelectric gate FETs, NEMS) using alternative channel, source/drain, and gate materials. We will present the main challenges to continue More's law, the novel materials and device architectures, and the possible combination of these boosters, needed for the development of future ultralow-power ICs.

show abstract

Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages

Cited by 97 publications

References 3 publications

A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current

A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Ultralow-Power Device Operation

Contact Info

Product

Resources

About