A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current

Zhang, Jian; Marchi, Michele De; Gaillardon, Pierre-Emmanuel; Micheli, Giovanni De

doi:10.1109/iedm.2014.7047045

Cited by 63 publications

(61 citation statements)

References 8 publications

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“…The symmetrical part 0 f of the BTE is obtained after substituting the explicit forms of the electric field and collision terms into equation (2). The details of the procedure are given in literatures [13,6] for lattice at room temperature.…”

Section: Analytical Formulation Of Btementioning

confidence: 99%

“…Hot carrier multiplication leads to avalanche breakdown in advanced scale bipolar devices, substrate current leakage in UTBOX FDSOI MOSFET [1] and the performance a Schottky-Barrier Silicon FinFET [2]. Impact ionization (II), which is the central generation process reliable for the breakdown, plays an important role in device degradation failure threshold in electrostatic discharge (ESD) protection and power devices.…”

Section: Introductionmentioning

confidence: 99%

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Temperature dependence of electron impact ionization coefficient in bulk silicon

Ahmed¹

2017

AIP Conference Proceedings

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This work exhibits a modified procedure to compute the electron impact ionization coefficient of silicon for temperatures between 77 and 800K and electric fields ranging from 70 to 400 kV/cm. The ionization coefficients are computed from the electron momentum distribution function through solving the Boltzmann transport equation (BTE). The arrangement is acquired by joining Legendre polynomial extension with BTE. The resulting BTE is solved by differences-differential method using MATLAB ® . Six (X) equivalent ellipsoidal and non-parabolic valleys of the conduction band of silicon are taken into account. Concerning the scattering mechanisms, the interval acoustic scattering, non-polar optical scattering and II scattering are taken into consideration. This investigation showed that the ionization coefficients decrease with increasing temperature. The overall results are in good agreement with previous experimental and theoretical reported data predominantly at high electric fields.

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Section: Analytical Formulation Of Btementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Temperature dependence of electron impact ionization coefficient in bulk silicon

Ahmed¹

2017

AIP Conference Proceedings

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“…Reference [9] showed that for a 50-μm-thick silicon fabric, the fracture stress is about 1.1 GPa. Substituting a (100) silicon Young's modulus of 128 GPa [10] in Equation (1), and the resulting strain value from Equation (2), we obtain a minimum bending radius for the 50-μm-thick flexible silicon fabric of approximately 3 mm, which decreases with a decreasing thickness. Therefore, a plain flexible silicon substrate that is 50-μm-thick or thinner with a bending radius of more than 3 mm will safely operate below the fracture stress level.…”

Section: A Silicon's Bending Ability and Limitationsmentioning

confidence: 99%

“…They must have low power consumption (dynamic and static), high performance, and flexibility. Subthreshold swing (SS) is a critical parameter to this end because it affects the switching speed of a transistor and its dynamic power consumption [1].…”

Section: Introductionmentioning

confidence: 99%

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

Ghoneim

Alfaraj

Torres-Sevilla

et al. 2016

IEEE Trans. Electron Devices

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“…Such transistors with CP have been successfully implemented in SiNWs [9], [10], carbon nanotube [26], graphene [27], and FinFET [28]. In such transistors, one electrode gate, the control gate (CG), works like conventional MOSFETS, and provides the conduction by controlling potential barriers.…”

Section: A Transistors With Cpmentioning

confidence: 99%

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Mohammadi

Gaillardon

Micheli

2015

IEEE Trans. Nanotechnology

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Abstract-Controllable-polarity silicon nanowire transistors (CPSiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at ntype, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.Index Terms-Controllable-polarity silicon nanowires, defect, fault model, gate oxide short, nanotechnology.

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A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current

Cited by 63 publications

References 8 publications

Temperature dependence of electron impact ionization coefficient in bulk silicon

Temperature dependence of electron impact ionization coefficient in bulk silicon

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

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