Ultralow-Power Device Operation

Abstract

The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition. We are facing today dramatic challenges dealing with the limits of energy consumption and heat removal, inducing fundamental tradeoffs for the future ICs. A substantial reduction of the static and dynamic power is strongly needed for the development of future high-performance/ultralow-power terascale integration and autonomous nanosystems.This chapter of the tutorial book addresses the main trends, challenges, limits, and possible solutions for strongly reducing the energy per binary switching. Several paths are possible, the most promising one being the reduction of static and dynamic energy consumption using conventional logic with a reduction in the stored energy and therefore a decrease of device capacitance C (device integration) and applied bias V, together with a decrease of leakage currents of nanodevices.The best potential solutions are ultrathin-film SOI (silicon-on-insulator) and multi-gate devices, nanowires, and small-slope switches (tunnel FETs, ferroelectric gate FETs, NEMS) using alternative channel, source/drain, and gate materials. We will present the main challenges to continue More's law, the novel materials and device architectures, and the possible combination of these boosters, needed for the development of future ultralow-power ICs.