Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

Kohler, Adan; Schley, Gert; Radetzki, Marian

doi:10.1109/tcad.2010.2048399

Cited by 80 publications

(51 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For functional testing of NoC, references [5][6][7] use data encoding in order to detect faults in the communication links and the switch datapath elements. Test repetition classifies the transient or permanent nature of the fault.…”

Section: Introductionmentioning

confidence: 99%

Structural Software-Based Self-Test of Network-on-Chip

Dalirsani

Imhof

Wunderlich

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test.

show abstract

Section: Introductionmentioning

confidence: 99%

Structural Software-Based Self-Test of Network-on-Chip

Dalirsani

Imhof

Wunderlich

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

show abstract

“…The aggregated traffic from other input channels in router and contends with dir in the output direction k F i,j X CQ [6 : 9] Forwarding probability from current channel i to four output directions CQ * X CQ [10] The estimated channel queuing time [18] The estimated source queuing time from the proposed queuing model S * X SQ [19] The estimated source service time from the proposed queuing model where g(s, d, k, i, j) is a binary indicator that returns 1 if the routing path P s,d…”

Section: Overall Svr-noc Methodologymentioning

confidence: 99%

“…2.7-b, the source traffic rate λ s as well as the waiting time CQ R1,W in the west down-streaming link are shown, which corresponds to X SQ [1] and X SQ [10] in Table 2.3, respectively. We present the ǫ-SVR formulation of the channel average waiting time function f CQ while similar procedures can be applied for obtaining f SQ .…”

Section: Source Queuing Feature Vectormentioning

confidence: 99%

“…A significant error tolerance to both permanent and temporary faults is thus strongly desired. Temporary errors are mainly due to the on-chip crosstalks and coupling noise while permanent faults are mostly caused by the worn-out devices, manufacturing defects and accelerated aging effects [10]. The NoC architecture offers a good opportunity of achieving high reliability since it provides multiple paths between the source-destination communication pairs and allows reconfiguration under faulty conditions.…”

Section: Introductionmentioning

confidence: 99%

“…However, a fine-grained functional fault model will be more beneficial because graceful degradation of network operation by exploiting the partially functional resources can be achieved [10]. In this chapter, we identify the major fault components in the NoC and propose a fine-grained permanent fault model, which distinguishes the partial router faults (buffer or crossbar faults) from the hard link faults.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Qian¹

View full text Add to dashboard Cite

TABLE OF CONTENTS Title Page i Authorization Page ii Signature Page iiiAcknowledgments iv Table of Contents v List of Figures ix List of Tables xiiiAbstract xiv Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bidirectional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel.We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the selfreconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

show abstract