Structural Software-Based Self-Test of Network-on-Chip

Dalirsani, Atefe; Imhof, Michael E.; Wunderlich, Hans-Joachim

doi:10.1109/vts.2014.6818754

Cited by 9 publications

(4 citation statements)

References 19 publications

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“…Alternatively, functional tests can be applied [1]. In reverse, structural faults can be diagnosed with functional techniques [16], and SAT-based ATPG can be employed to ensure high structural coverage of functional software-based self-test (SBST) [10]. Like on other layers, concurrent error detection with error detecting codes (e.g.…”

Section: Network Layermentioning

confidence: 99%

Multi-Layer Test and Diagnosis for Dependable NoCs

Wunderlich

Radetzki

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining faultfree functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.

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Section: Network Layermentioning

confidence: 99%

Multi-Layer Test and Diagnosis for Dependable NoCs

Wunderlich

Radetzki

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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“…Aisopos et al [14] propose a modeling of variation-induced faults in NoCs to study the impact of delay faults at the system level. In [15], a software-based self-test approach generates test patterns targeting structural faults where the switch under test still must go to the test mode.…”

Section: A State Of the Artmentioning

confidence: 99%

“…The combinational core of the switch, Φ c , is transformed to a conjunctive normal form (CNF) using the Tseitin transformation [21]. The sequential behavior of the switch, Φ T s , is modeled by time-frame expansion of Φ c , as in [15]. The literals of the PPIs of each copy are connected to the literals of the PPOs of the previous copy in the SAT instance, as shown in Fig.…”

Section: Structural Fault Injection Mechanismmentioning

confidence: 99%

On Covering Structural Defects in NoCs by Functional Tests

Dalirsani

Hatami

Imhof

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering structural faults. The method targets NoC switches and links, and it is independent of the switch structure and the network topology. It can be applied for any structural fault type as it relies on a generalized structural fault model.

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“…Some other researchers have tried to invent new methods for functional testing of certain modules in complex processors [19,20]. Some others have tried to use SBST techniques to test non-processing components of a system such as main memory system, cache memory subsystem, or interconnections [21][22][23][24]. A lot of researches have recently focused on providing proper SBST techniques to test emerging multiprocessor systems [25][26][27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

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Structural Software-Based Self-Test of Network-on-Chip

Cited by 9 publications

References 19 publications

Multi-Layer Test and Diagnosis for Dependable NoCs

Multi-Layer Test and Diagnosis for Dependable NoCs

On Covering Structural Defects in NoCs by Functional Tests

HASTI: hardware‐assisted functional testing of embedded processors in idle times

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