On Covering Structural Defects in NoCs by Functional Tests

Dalirsani, Atefe; Hatami, Nadereh; Imhof, Michael E.; Eggenberger, Marcus; Schley, Gert; Radetzki, Marian; Wunderlich, Hans-Joachim

doi:10.1109/ats.2014.27

Cited by 6 publications

(1 citation statement)

References 18 publications

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“…The human designer may not be able to consider all possible temporal interactions between the complex logic circuitry and inputs of a circuit design, especially early in the design stage, and cannot guarantee full concordance of a design with user specifications. Functional and formal design verification are iterative processes that help the designer build confidence in the design [1,2]. These processes include debugging to find logic errors and behaviours that utilize deep neural networks via deep learning as a new methodology to design digital circu its.…”

Section: Introductionmentioning

confidence: 99%

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Yeong,

2023

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Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

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Section: Introductionmentioning

confidence: 99%