Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Charif, Amir; Busnot, Gabriel; Mameesh, Rania; Sassolas, Tanguy; Ventroux, Nicolas

doi:10.1145/3300189.3300192

Cited by 29 publications

(12 citation statements)

References 14 publications

(12 reference statements)

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“…As a proof of concept, the NoC performance model was integrated in a FSS called VPSim [3]. VPSim is a SystemC/TLMbased virtual prototyping platform for fast software/hardware co-validation and design space exploration of complex architectures, fast being the operative word.…”

Section: B Noc Model In Full System Simulationmentioning

confidence: 99%

“…This comparison was performed in terms of simulation speed and average network latency using different synthetic traffic patterns. We also integrated our NoC model in a fast FSS environment called VPSim [3] supporting a 32-core architecture configuration with a 6×6 mesh and a 3level cache hierarchy and we evaluated its impact on the overall simulation speed.…”

Section: Introductionmentioning

confidence: 99%

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NoC Performance Model for Efficient Network Latency Estimation

Matoussi

2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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We propose a flexible light-weight and parametric NoC model designed for fast performance estimation at early design stages. Our NoC model combines the benefits of both analytical and simulation-based NoC models. Our NoC features an abstract router model whose buffers are updated at runtime with information about the actual traffic. This traffic information is fed to a closed-form expression that computes packet latency and that accounts for network contention at a router basis. We evaluated our hybrid NoC model in terms of estimation accuracy and simulation speed. We compared the simulation results to the ones obtained with a cycle accurate NoC simulator called Garnet. Our NoC model achieves less than 17% error in average network latency estimation and attains up to 14× speedup for a 8×8 mesh.

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Section: B Noc Model In Full System Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

NoC Performance Model for Efficient Network Latency Estimation

Matoussi

2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…Different levels of abstraction can be employed for each part of the system, according to the required accuracy/speed trade-off. In [86] a RISC-V virtual prototype is described, and in [87] a RISC-V virtual prototype is reported to be in the range of 30-220 MIPS (depending on the accuracy).…”

Section: Simulation Modelsmentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systems could benefit from many of those developments, and this work identifies and highlights what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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“…As their model is cycle-accurate, it offers visibility close to RTL simulation but with a very slow performance. Other works propose to use a processor emulator such as QEMU to provide an accurate and realistic CPU model [6,7]. The integration of QEMU to emulate the processors and TLM to model the hardware modules results in a fast co-simulation method in exchange for cycle accuracy.…”

Section: Related Workmentioning

confidence: 99%

“…In this work, the virtual platform is built using VPSim [7]. VPSim is an existing tool, part of the SESAM EDA framework, which is used for virtual prototyping and Design Space Exploration (DSE).…”

Section: A Virtual Prototyping Toolmentioning

confidence: 99%

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design

Wicaksana

Charif

Andriamisaina

et al. 2019

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)

Self Cite

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As the System-on-Chip (SoC) complexity increases, hardware/software co-design plays an important role to improve design productivity, reduce time to market, and optimize the overall results. Consequently, there is a high interest in providing rapid system validation in such a paradigm to achieve the aforementioned objectives. There exist in previous works prototyping techniques related to the development phase. FPGA-based prototyping has the benefits of enabling HW/SW integration and system validation after the Register Transfer Level (RTL) implementation is available while virtual platforms provide capabilities to accelerate software development with higher level functional models, e.g. Transaction Level Modeling (TLM). In this paper, we propose a hybrid prototyping methodology which takes advantage of virtual and FPGA-based prototyping in a single framework. We aim to provide a rapid and flexible system validation solution for HW/SW co-design at various stages of development based on the availability of TLM and RTL implementations. The proposed methodology allows online and offline performance analysis and debugging for early feedback in HW/SW architecture exploration. This was evaluated in the experiments with a neural network processor as a case study.

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Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Cited by 29 publications

References 14 publications

NoC Performance Model for Efficient Network Latency Estimation

NoC Performance Model for Efficient Network Latency Estimation

Leveraging the Openness and Modularity of RISC-V in Space

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design

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