NoC Performance Model for Efficient Network Latency Estimation

Matoussi, Oumaima

doi:10.23919/date51398.2021.9474101

Cited by 9 publications

(4 citation statements)

References 14 publications

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“…In the event of a simulation error, the results of all the following phases are discarded as unsatisfactory to the technical specifications, and the simulation is performed again. At the same time, it is at the phase of behavioral modeling that a description of the system being developed is formed, and its components and their characteristics are determined [21].…”

Section: Figure 5 Phases Of the Noc Design Flowmentioning

confidence: 99%

Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

Lezhnev,

Zunin,

Amerikanov

et al. 2024

IEEE Access

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This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic control system. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.INDEX TERMS electronic computer-aided design (ECAD), HDL, network-on-chip (NoC), modeling, RTL.

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Section: Figure 5 Phases Of the Noc Design Flowmentioning

confidence: 99%

Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

Lezhnev,

Zunin,

Amerikanov

et al. 2024

IEEE Access

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“…Fairly benchmarking communication networks is a rather tedious and time-consuming process that requires long simulation times for properly assessing the interconnect behavior. Analytical models are a viable alternative for conventional NoC designs, and recent contributions [25] have even shown the opportunity of combining analytical models with simulations. Yet given the unconventional nature of R-NoC, we perform RTL and postsynthesis gate-level simulations for unbiased performance assessment.…”

Section: R-noc Evaluationmentioning

confidence: 99%

Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect

2022

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Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform traffic patterns thus leading to performance degradation for such applications. To improve network performance, the Roundabout NoC (R-NoC) concept is considered. R-NoC is inspired by real-life multi-lane traffic roundabouts and consists of lanes that are shared by multiple input/output ports to maximize buffering resource utilization. R-NoC relies on router-internal adaptive routing that decides the lane path based on back pressure. Back pressure makes it possible to assess lane utilization and route packets accordingly. This is made possible thanks to the use of elastic buffers for control flow, a clever type of handshaking in a way similar to asynchronous circuits. Another prominent feature of R-NoC is that internal routing and arbitration are completely distributed which allows for significant freedom in deciding internal router topology and parameters. This work leverages this property and proposes novel yet unexplored configurations for which an in-depth evaluation of corresponding implementations on 45 nm CMOS technology is given. Each configuration is evaluated performance and power-wise on both synthetic and real application traffic. Several R-NoC configurations are identified and demonstrated to provide very significant performance improvements over standard mesh configurations and a typical input-buffered router, without compromising area and power consumption. Exploiting the distributed nature of R-NoC routers, a diagonally-linked configuration is then proposed which incurs moderate area overhead and features yet better performance and energy efficiency.

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“…The reference model of SESAM/VPSim explores the behavior of larger systems ranging from 32 to 64 cores, modelled using QEMU Arm V8.4-A ISA. The existing memory hierarchy was extended to evaluate consistency traffic with an MSI protocol and included a hybrid NoC model [33] able to account for network congestions based on simulated traffic. The model was validated against Garnet for its accuracy.…”

Section: E Architectural Exploration and Setupmentioning

confidence: 99%

Multilevel simulation-based co-design of next generation HPC microprocessors

Zaourar

Benazouz

Mouhagir

et al. 2021

2021 International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS)

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This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-level cache (SLC) size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable sufficient accuracy without having to resort to highly detailed simulations. Then we apply gem5, a cycle-accurate micro-architecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study the network-on-chip (NoC) topology and IP placements using both gem5 for representative small-to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details. Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings. We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns and evaluate them to guide architectural design and optimization decisions. Performance analysis is carried out with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SIMD instruction width, SLC sizing, memory bandwidth as well as the best placement of memory controllers and NoC form factor. Thus, we provide critical insights for efficient design of future HPC microprocessors.

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NoC Performance Model for Efficient Network Latency Estimation

Cited by 9 publications

References 14 publications

Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect

Multilevel simulation-based co-design of next generation HPC microprocessors

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