Fast Transient Fully Standard-Cell-Based All Digital Low-Dropout Regulator With 99.97% Current Efficiency

Akram, Muhammad Abrar; Hong, Wook; Hwang, Inseok

doi:10.1109/tpel.2017.2771942

Cited by 41 publications

(22 citation statements)

References 23 publications

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“…From the above analysis, the current I MPS should be at least ∼10 mA. Accordingly, the current generator adopts LDO architecture to improve the driving capability and will be activated by the andgate AND2 when the T O and EN1 are both high level [18][19][20][21][22]. Moreover, one technique is to add a PMOS P1 to ensure that the voltage at point B strictly follows the voltage reference V Ref1 .…”

Section: System Overviewmentioning

confidence: 99%

Adaptive maintain power signature scheme for power over ethernet system

Zhu

2020

IET Power Electronics

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Power over Ethernet (PoE) technology has been widely used in networking market for its space-saving, flexibility and low cost. As the PoE system needs to meet maintain power signature (MPS) requirements specified by the IEEE standard, it is important for powered device (PD) to draw a predetermined minimum current. If the PD current goes below the minimum current, the power sourcing equipment (PSE) assumes the PD has been disconnected and terminates operating voltage. If a fixed current is added to exceed the minimum current, a phenomenon of power wasting will be caused during standby or ultralow power mode. This study proposes an adaptive MPS scheme to achieve power-saving and meet the MPS requirements. It consists of current comparator and MPS circuit to extract the periodic pulsed current for MPS requirements. The proposed scheme has been fabricated in 0.18 μm 100 V Bipolar-CMOS-DMOS process adding no extra pin and an area is 1.45 × 2.23 mm 2. Test results show that the proposed interface sources a periodic pulsed current with a period of 318 ms and 25% duty cycle to tackle the issue of MPS absence in very low power condition.

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Section: System Overviewmentioning

confidence: 99%

Adaptive maintain power signature scheme for power over ethernet system

Zhu

2020

IET Power Electronics

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“…Digital low-dropout (D-LDO) regulators are used in portable devices, biomedical devices, and internet-of-things applications [1][2][3][4][5][6][7][8][9][10] because of their lower supply-voltage, small power-transistors, stability, and compatible processes. However, D-LDO features a long settling time and a ringing problem while settling the output voltage at large load transitions.…”

Section: Introductionmentioning

confidence: 99%

“…Several D-LDOs have been developed to reduce settling time [2][3][4][5][6][7][8][9][10][11][12] and D-LDOs with proportional-integral (PI) control removed the ringing. These devices used a level-crossing ADC with numerous reference voltages [2] and a delay line ADC with an analog voltage-to-current converter [3].…”

Section: Introductionmentioning

confidence: 99%

“…To prevent the large ringing, the coarse‐fine D‐LDO requires a guard time, the maximum possible settling time, to reactivate fine mode and stop the coarse mode, thereby increasing the overall time needed. In 8, the D‐LDO reduces the transient response time by using a variable‐gain accumulator, but exhibited a large undershoot voltage. Herein, a newly proposed coarse‐fine D‐LDO removes the ringing and reduces settling time by adding an auxiliary power stage.…”

Section: Introductionmentioning

confidence: 99%

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Low‐ripple coarse‐fine digital low‐dropout regulator without ringing in the transient state

Woo

Yang

2020

ETRI Journal

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Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μm 2. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 μs to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 μA.

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“…These techniques result in an increased circuit complexity, power consumption and area. In D-LDO, the most important challenges are to limit the output ripples during steady-state time, reduce the quiescent current, diminish the output voltage spikes and minimize the response time during the transition period [23].…”

Section: Introductionmentioning

confidence: 99%

A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications

et al. 2020

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In this paper, a high performance adaptive digital low-dropout voltage regulator (ADLDO) is proposed for Internet-of-Things (IoT) applications. In the proposed ADLDO, a fully synthesizable adaptive digital controller is designed. It automatically senses load variations and adaptively controls multi-loop architecture to reduce quiescent current, minimize output voltage ripples and achieve fast transient response. The multi-loop architecture with hill climbing reduces the total bi-directional shift registers length which results in the reduced leakage current in the transistor-switch-array (TSA), and improves the recovery time and output DC voltage accuracy. A dithering technique is introduced to eliminate the limit cycle oscillation (LCO) and improve the performance of the regulator. The dynamic frequency scaling (DFS) mechanism is proposed for reducing controller power consumption in steady state. In order to reduce the offset and output voltage error, a dynamic latch comparator is utilized. When the input supply voltage is varied from 0.5 V to 1 V, the measured output voltage ranges from 0.45 V to 0.95 V with 50 mV dropout voltage. The operating frequency is 10 MHz with fast transient response and quiescent current of 350 ns and 3.7 μA, respectively. The maximum measured power and current efficiencies are 89.7 % and 99.97 %, respectively, with 1.9 mV output voltage ripples. Measured load and line regulations are 2.2 mV/mA and 9.5 mV/V respectively. The proposed circuit is implemented in 28 nm CMOS process and occupies 0.016 mm 2 chip area. INDEX TERMS Adaptive, dithering, digital LDO, dynamic frequency scaling (DFS), fully synthesizable, fast transient, hill climbing, limit cycle oscillation (LCO), low power, multi-loop.

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Fast Transient Fully Standard-Cell-Based All Digital Low-Dropout Regulator With 99.97% Current Efficiency

Cited by 41 publications

References 23 publications

Adaptive maintain power signature scheme for power over ethernet system

Adaptive maintain power signature scheme for power over ethernet system

Low‐ripple coarse‐fine digital low‐dropout regulator without ringing in the transient state

A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications

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