Fast test generation for sequential circuits

On static compaction of test sequences for synchronous sequential circuits

“…The same applies to all the other faults with detection times 9 and lower. The first pass over all the faults terminates with omitted [2] …”

“…In the worst case, it will terminate after restoring all the test vectors of the original sequence. In our example, all the faults are detected by the sequence with omitted [2] …”

“…In addition, we set omitted [2] = omitted [3] = omitted [6] = omitted [9] = omitted [10] = 0 since at least one fault is detected in these time units.…”

“…During the vector omission procedure, test vectors are omitted from the test sequence one at a time or in subsequences. It was shown that the level of compaction achieved by this technique is significant for test sequences generated by various deterministic test generation procedures such as [2] and [3]. However, since the omission of each vector or subsequence requires resimulation of the test sequence to ensure that the fault coverage does not go down, the run time of the omission procedure from [1] is relatively high.…”

“…This suggests that it may be faster to decide which test vectors must be restored into the test sequence in order to maintain the fault coverage, instead of deciding on the test vectors that may be omitted. (2) The effort required to decide whether a test vector needs to be restored is lower than the effort required to decide that a test vector can be omitted. To omit a vector, one must ensure that no detected fault becomes undetected after the omission.…”