On static compaction of test sequences for synchronous sequential circuits

Pomeranz, I.; Reddy, S.M.

doi:10.1109/dac.1996.545575

Cited by 12 publications

(25 citation statements)

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“…Finally, both vector-restoration [6, 71 and our proposed techniques are not constrained by lack of recurrence subsequences and can produce compact test sets a t less expensive costs than [3]. One significant feature about our technique is that the test-set and fault-list partitioning strategy can be applied to any of the previously proposed vector-omission [3] and vector-restoration [6, 71 methods to further reduce execution times. This is an important feature that distinguishes our technique from the previously proposed methods.…”

Section: Resultsmentioning

confidence: 87%

“…Furthermore. [3] generally outperforms other compaction approaches a t high computation costs. However.…”

Section: Resultsmentioning

confidence: 99%

“…Some of these approaches [l, 21 cannot reduce test sets produced by random or simulationbased test generators. Static compaction techniques based on vector insertion, omission, or selection have been investigated [3]. These techniques require multiple fault simulation passes.…”

Section: Introductionmentioning

confidence: 99%

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Partitioning and reordering techniques for static test sequence compaction of sequential circuits

Hsiao

Chakradhar²

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

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static test set compaction based on removing recurrence subsequences that start and end on the same or similar states has been reported recently [4. 51. Though fast, these test sets are not as compact as those achieved by algorithms that use multiple fault simulation passes. The curve with a small dip is associated with test sets that are composed of random vectors followed by vectors generated using automatic test pattern generators (ATPG's), while the W e propose Q new statzc test set compactzon method based o n a careful e.camznatzon of attrzbutes of fault coverage curves. Our method zs based o n two k e y zdeas: ( 1 ) fault-lzst and testset partztzonzng, and (2) vector re-orderzng. Typzcally, the first f e w vectors of a test set detect a large number of f Q U k 9 . T h e remaznzng vectors usually constztute a large fractzon of the test set, but these vectors are zncluded to detect relatzvely f e w hard faults. W e ahow that szgnzficant compactzon can be Figure 1 shows two typical fault coverage curves. achieved by partitzoning faults i n t o hard and easy faults. This significantly reduces the computational cost for statzc test set compaction wzthout affecting quality of compaction. T h e second technique re-orders vectors i n a test set by moving sequences that detect hard faults to the begznnzng of the test set. Fault simulatzon of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller t h a n the original test set. Experiments o n several ISCAS 89 sequential benchmark czrcuits and large production czrcuits show that our compaction procedure yields significant test set reductions in low execution times.

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Section: Resultsmentioning

confidence: 87%

“…Furthermore. [3] generally outperforms other compaction approaches a t high computation costs. However.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Partitioning and reordering techniques for static test sequence compaction of sequential circuits

Hsiao

Chakradhar²

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

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“…We use the following omission-based static compaction procedure [8] Given a random partitioning of the vectors of T G into subsets S 1 ,S 2 , . .…”

Section: Additional Results Of Test Generationmentioning

confidence: 99%

“…Suppose that u sync = 2. We represent Z as (2,3,3,2,2,2,8,8). Here, the first 2 stands for z 2 = 000, and the following 2's stand for z 5 , z 6 and z 7 which are equal to z 2 .…”

Section: Properties Of Output Sequencesmentioning

confidence: 99%

Properties of output sequences and their use in guiding property-based test generation for synchronous sequential circuits

Pomeranz

Reddy

Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002

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We show that output sequences produced by synchronous sequential circuits in response to test sequences that achieve high fault coverage have certain distinct properties. We demonstrate that these properties are useful as part of a property-based (simulation-based) test generation procedure. The importance of these properties is that they provide additional heuristics to drive property-based test generation, which to-date achieves the highest fault coverages reported for benchmark circuits. These additional heuristics are expected to improve the ability of propertybased test generation procedures to achieve complete fault coverage in an efficient manner.

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Functional Compaction for Functional Test Sequences

Pomeranz

2024

IEEE Access

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On static compaction of test sequences for synchronous sequential circuits

Cited by 12 publications

References 10 publications

Partitioning and reordering techniques for static test sequence compaction of sequential circuits

Partitioning and reordering techniques for static test sequence compaction of sequential circuits

Properties of output sequences and their use in guiding property-based test generation for synchronous sequential circuits

Functional Compaction for Functional Test Sequences

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