Fast comparisons of circuit implementations

Karandikar, S.K.; Sapatnekar, Sachin S.

doi:10.1109/tvlsi.2005.862727

Cited by 9 publications

(6 citation statements)

References 16 publications

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“…However, modernday VLSI circuits behave in a non-linear manner for which this algorithm is unable to yield optimal performance. Transistor sizing methods in [19,33,71] present a simple but effective way of determining transistor sizes for delay optimization. However, only the critical path is considered in these two methods, for which power consumptions of circuits are not optimized.…”

Section: Transistor Sizingmentioning

confidence: 99%

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

et al. 2021

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Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness.

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Section: Transistor Sizingmentioning

confidence: 99%

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

et al. 2021

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“…The transistor sizing problem is formulated as a constrained nonlinear mathematical program of optimization factors. MDE (Minimum Delay Estimation) and ADC (Area-Delay Curve) algorithms [22] are within this group. Another approach is a Heuristic approach which was proposed for the first time in TILOS [14].…”

Section: Vlsi Designmentioning

confidence: 99%

“…Two algorithms, MDE and ADC, which are dealt with, are based on logical effort. The work [22] shows how these algorithms can size the transistors without running a heuristic sizing tool by calculating the minimum achievable delay and the cost of achieving a target delay.…”

Section: Transistor Sizing Based On Logical Effortmentioning

confidence: 99%

“…The most significant point in this algorithm is that the minimum achievable delay is computed for all fan-out paths of a transistor. MDE algorithm obtains the Delay-C in curve (C in is the input capacitance of a circuit) based on some formulas as in [22].…”

Section: Mde Algorithmmentioning

confidence: 99%

“…According to the pseudocode in [22], the execution time of ADC is O(N), where N is transistor count.…”

Section: Adc Algorithmmentioning

confidence: 99%

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Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

et al. 2010

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A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP), chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 μm technology based on the BSIM3v3 model using HSpice simulator software.

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Performance of Adders with Logical Optimization in FPGA

Uma

Dhavachelvan

2012

Advances in Intelligent and Soft Computing

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Fast comparisons of circuit implementations

Cited by 9 publications

References 16 publications

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Performance of Adders with Logical Optimization in FPGA

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