Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Abstract

A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP), chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 μm technology based on the BSIM3v3 model using HSpice simulator software.

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

“…In an alternative strategy, a ferromagnet with the same size but different material may be used to enforce a similar effect. The possible practical demonstrations for this action can be stated as follows: (1) inside the untrusted foundry by physical intrusion, (2) doing modifications within the algorithms used for sizing the design cells, and (3) inserting a few maliciously constructed cells in the process of IC design flow [130,131]. The impact of this attack can be observed as the occurrence of logical transitions of the MTJ device earlier or later than the expected time.…”

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

“…On the other hand, if it is set to a value such as 0.67 × V DD , all the circuit/system elements along with the Hardware Trojan are active. There are a number of possibilities for performing the malicious cell sizing: (1) physically inside the untrusted foundry; (2) applying malicious modifications within the algorithms utilized for sizing the design cells; and (3) designing a few malicious cells and inserting them inside the chip during application specific integrated circuit (ASIC) design flow [30][31][32][33][34]. Adjusting the supply voltage can be done internally through predefined circuit/system conditions or externally by a malicious person.…”

A Low Cost circuit level fault detection technique to Full Adder design

“…It is probable that without any switching activity at the output node, some internal nodes experience logic changes, during imposing input patterns. Consequently, in order to have an accurate fault diagnosis result, all the possible input combinations are considered to test circuits [16] [11]. Therefore, input test patterns which offer all possible transitions from one input combination to another are used as the input vectors for the FA circuit.…”

“…By this way a fair judgment on power consumption of the error detector circuit has been gathered with respect to other parts of the circuit. We used Simple Exact Algorithm (SEA) [16] for transistor sizing the proposed FA circuit, where transistors that have almost the same role in the circuit are grouped together. For calculating PDP parameter, which is the targeting parameter in this algorithm, total average consumption power during the whole operating time (560 ns) is being reported.…”