A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP), chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 μm technology based on the BSIM3v3 model using HSpice simulator software.
Optimization of multiprocessor systems relies heavily on the efficient design of on-chip routing algorithms. Adaptive routing appears to have an extremely significant role in the performance of the Networks-on-Chip. In this paper, a deadlock-free and highly adaptive minimal routing method (HOE) is proposed. Although the Hamiltonian Adaptive Multicast Unicast Model (HAMUM) is able to support a high degree of adaptiveness, it cannot exploit some of the potential alternative paths in routing. By prohibiting the minimum number of turns, our proposed method strives to find the maximum number of alternative paths between each pair of source and destination nodes, without using virtual channels. HOE has also been applied to the ColumnPath (CP) routing algorithm to improve its characteristics. The simulation results validate the flexibility of our approach in choosing the appropriate routing path depending on the congestion condition of the network. The better performance of the proposed method is due to its higher degree of adaptiveness which results in less vulnerability to nonuniform factors and a better traffic distribution all over the network.
With the aggressive scaling of the VLSI technology, Networkson-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient NoCs is of significant importance. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. Moreover, they cannot adapt to the dynamic traffic distribution in the network. Considering the increasing demands for real-time systems, the necessity for designing reconfigurable and robust NoCs is even more pronounced. In this paper, a dynamically reconfigurable technique is proposed to address faulttolerance and minimal routing in mesh NoCs. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.
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