Failure Analysis of Asymmetric Aging Under NBTI

CSAM: A clock skew-aware aging mitigation technique

“…The results show that on average the lifetime increases 34% compared to the conventional technique while the best (worst) corresponds to 77% (4%). Next, we study the results for the second objective function formulated in (10). In this case, first, for each benchmark, we solved the optimization problem using the conventional approach.…”

“…If, however, the gating technique is invoked, the asymmetric aging causes some additional clock skew in the network. The effects of asymmetric aging due to usage of clock gating schemes are discussed in [9,10,[13][14][15].…”

“…This causes asymmetric aging rate which induces a non-uniformity in the timing rendered by the clock tree at different parts of the chip. The effects of asymmetric NBTI induced aging on the reliability (lifetime) of the logic path and clock tree circuits have been studied and techniques to improve the reliability have been suggested (see, e.g., [9,10]). To the best of our knowledge, these techniques, however, have focused either only on the logic path (neglecting the NBTI effect on the clock tree part) or on the clock tree part (ignoring the NBTI effect on the logic path circuit).…”

Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

“…The models, however, were complicated as they used the Taylor series expansion and Chebyshev polynomial to fit the gate delay degradation. The works presented in [11] and [12], used the upper bound of the NBTI delay degradation, given in [3], to predict the timing violations of the combinational logic path under the NBTI-induced asymmetric aging. In [11], the aginginduced gate delay degradation for the library cells was formulated as a function of the threshold and supply voltages.…”

“…The works presented in [11] and [12], used the upper bound of the NBTI delay degradation, given in [3], to predict the timing violations of the combinational logic path under the NBTI-induced asymmetric aging. In [11], the aginginduced gate delay degradation for the library cells was formulated as a function of the threshold and supply voltages. The expression then was used to calculate the degradation as a function of the threshold voltage shift without relying on the time consuming circuit simulations.…”