Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

Eghbalkhah, B.; Kamal, Mehdi; Afzali-Kusha, Hassan; Afzali-Kusha, Ali; Ghaznavi‐Ghoushchi, M. B.; Pedram, Massoud

doi:10.1016/j.microrel.2015.06.004

Cited by 7 publications

(6 citation statements)

References 17 publications

(38 reference statements)

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“…Accordingly, some researchers have carried out works predicting the lifetime of transistors under dynamic operation voltage (DOV), as shown in Table II (See [32], [38], [40]- [44] for more details). These models could be broadly divided into two categories.…”

Section: B Aging Model Under Dynamic Stressmentioning

confidence: 99%

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Development and Challenges of Reliability Modeling From Transistors to Circuits

Yang

Sang

Wang

et al. 2023

IEEE J. Electron Devices Soc.

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The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.

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Section: B Aging Model Under Dynamic Stressmentioning

confidence: 99%

“…Based on these steps, in [44], [60], a simulation framework for studying the NBTI-induced delay degradation in circuits was discussed. As shown in Fig.…”

Section: Circuit Reliability Analysis Based On Transistor Aging Modelmentioning

confidence: 99%

Development and Challenges of Reliability Modeling From Transistors to Circuits

Yang

Sang

Wang

et al. 2023

IEEE J. Electron Devices Soc.

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“…This partially recoverable nature of BTI poses some interesting challenges for the power/thermal/performance management of circuits as the duration of sleeping periods can impact BTI degradation and the overall system's reliability. Recent work shows the importance of the impact of temperature transients on BTI [ 65 ], whereas the previous observation implies that taking into account both, application characteristics and transient temperature on BTI modeling, 95:7…”

Section: Thermalmentioning

confidence: 99%

Predictive Reliability and Fault Management in Exascale Systems

et al. 2020

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Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due to the exponential increase in the number of devices per chip, to higher system fault rates. Consequently, High-performance Computing (HPC) systems need to integrate prediction, detection, and recovery mechanisms to cope with faults efficiently. This article reviews fault detection, fault prediction, and recovery techniques in HPC systems, from electronics to system level. We analyze their strengths and limitations. Finally, we identify the promising paths to meet the reliability levels of Exascale systems.

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“…Here, the factor n takes into account the variations in the bulk charge along the channel, VG=V gs -V th , W is the channel width, C ox is the gate oxide capacitance per unit area, V(x) is the potential difference between minority carrier quasi-Fermi potential and equilibrium Fermi potential in the bulk at point x and υ(x) is the carrier velocity at point x. The velocity versus electric field for electrons in the inversion layer is described as: (2) where υ sat is saturation velocity (m/s), E is the lateral electric field, M is a empirical constant and E c is the critical field at which the carriers are velocity saturated. It is widely accepted in literature that M = 2 for electrons and M = 1 for holes.…”

Section: Model Derivationmentioning

confidence: 99%

“…On the other hand, in low power logic circuits, the drive current is in the moderate inversion region. Process and environment variations affect device characteristics of MOSFETs, thereby varying the performance of integrated circuits [2]. One of the major challenges in robust and reliable circuit design lies in faithfully addressing analytically the effect of temperature variation [3].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model

Kalra¹,

Bhattacharyya²

2020

JICS

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Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.

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Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

Cited by 7 publications

References 17 publications

Development and Challenges of Reliability Modeling From Transistors to Circuits

Development and Challenges of Reliability Modeling From Transistors to Circuits

Predictive Reliability and Fault Management in Exascale Systems

An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model

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