Reliability prediction with MTOL

Abstract

Here, we develop a comprehensive reliability prediction of FPGA devices from data motivated by physics of failure. The Multiple Temperature Operational Life (MTOL) testing method was used to calculate the failure in time (FIT) of 3 different mechanisms on both 45 nm and 28 nm technologies. We confirmed that there is significant hot carrier injection (HCI) at sub-zero temperatures in 45 nm technology. Surprisingly, we found that 28 nm exhibits no HCI degradation even with up to 1.6 V on the core. As a result, we show that there is no effect of frequency on the reliability. This means that at 28 nm and possibly smaller technologies, the devices can be de-rated or up-rated based only on the NBTI model and therefore reliability is dependent only on operating Voltage and Temperature with a single activation energy. Notably, the activation energies and voltage acceleration factors for both technologies are remarkably similar. This demonstration shows that, unlike other conventional qualification procedures, the MTOL testing procedure gives a broad description of the reliability from sub-zero to high temperatures. This procedure provides FIT prediction which can be applied to newer technologies, specifically 20 nm and 16 nm and beyond.

A New Methodology for EMC Prediction of Integrated Circuits After Aging

“…Normally, four stress conditions should be defined to extract the reliability matrix P according to (4) since CMOS ICs are affected by four main degradation mechanisms, as explained in Section III. However, as shown in [20], TDDB is insignificant in this CMOS 45-nm technology. Its influence is neglected in this study so the number of stress conditions can be limited to three.…”

“…It requires the definition of a failure or degradation criterion by the experimenter. For example, in [20], it was computed according to a degradation criterion which defined as the drift of the propagation delays of a digital IC. Matrix AF contains the acceleration factors (A i , B i , C i , D i ) associated to the degradation mechanisms, which are computed according to models given in [16].…”

“…The new reliability prediction methodology was developed and validated on DSM commercial components designed in 28 and 45 nm technologies [20]. We can assume that for the same CMOS technology embedded in two different components, the degradation mechanisms activated by a multi-stress of voltage and temperature will be similar.…”

“…The circuit under test is a XC6SLX16-FT256 Spartan 6 Xilinx FPGA, manufactured in CMOS 45-nm process. M-STORM model was developed for this technology previously [20]. The circuit includes 9152 configurable logic blocks (CLB) and up to 186 user IOs.…”

Microelectronic reliability models for more than moore nanotechnology products

“…[58], is its success in separating different failure mechanisms in devices in such a way that actual reliability predictions can be made for any user defined operating conditions. This is opposed to the common approach for assessing device reliability today is the High Temperature Operating Life (HTOL) testing [59], which is based on the assumption that just one dominant failure mechanism is acting on the device [31].…”