Microelectronic reliability models for more than moore nanotechnology products

Abstract

To cite this version:Alain Bensoussan. Microelectronic reliability models for more than moore nanotechnology products. Facta Universitatis, Series: Electronics and Energetics, 2017, vol. 30 (n°1)

Time Resolved Hyperspectral Quantum Rod Thermography of Microelectronic Devices: Temperature Transients in a GaN HEMT

“…For the TTR measurements a thermo-reflectance coefficient calibration of Cth=4.25×10 -2 ±2.97×10 -3 was extracted as shown in Fig. 5 with the reflectivity change using (2). Cth is typically in the 10 -2 -10 -5 o C -1 range, depending on the material, illumination wavelength, optical set-up and surface roughness [19].…”

“…vital for an efficient and reliable device and circuit operation as device life time and operation is highly temperature dependent [1,2]. Temperature measurements are therefore critical to support device designs and for device lifetime estimations; they are also commonly used as an input parameter for compact electro-thermal modeling [3].…”

The Relationship between Entropy and the Reliability Function in Application of Physical and Statistical Approach to Nanosystems

“…where ( ) R t is the reliability function [9], R V is the region of validity, i.e. the device is functional when…”

Coupling simulation and accelerated degradation model for reliability estimation: Application to a voltage regulator

“…Previous studies on extracting accurate reliability modelling for ICs have considered multiple failure mechanisms by conducting multiple temperature operating lifetime (MTOL) method under multiple simultaneous stress conditions [8]. Multi-stress predictive reliability model (M-STORM) is developed considering different combinations of temperature and voltage stresses applied on FPGA circuits to accurately evaluate and predict the IC failure rate and time to failure (TTF) under any specified operating conditions [1,9]. Depending on the multiple stress conditions, the MTOL method enables to distinguish and identify different failure degradation mechanisms inducing on the CMOS circuits during accelerated ageing tests [10,11].…”