Facelift: Hiding and slowing down aging in multicores

Enhancing the L1 Data Cache Design to Mitigate HCI

“…Results were gathered just for the memory cell with the highest number of flips (not necessarily the same cell across the studied approaches), which is the one that suffers the highest HCI wearout. Results have been computed using a standard dV th formula [8] and assuming a 3-year lifetime for our 32nm technology node [3]. To complete this execution period, we have assumed that the simulated amount of 500M instructions is repeated over and over until the established period is reached.…”

“…The former effect increases with transistor activity over the lifetime of the processor; that is, when the cell contents flip from logic '0' to '1' and vice versa, leading to threshold voltage (V th ) degradation (∆V th ∝ p active time × num flips/num cycles) [8], which in turn causes an increase in transistor switching delay (∆Delay ∝ 1/(V dd − ∆V th ) α , α > 1) [8] and can result in faulty operation. On the other hand, BTI accelerates the cell degradation when a given logic value is stored for a long time.…”

“…Other work [6] modified the original SRAM cell design used to implement the issue queue. Finally, in [8], Tiwari and Torrellas dynamically adapt the effects of temperature and voltage on aging to enlarge the processor lifetime. However, to the best of our knowledge, there is no previous work at architectural level addressing HCI aging in caches.…”

A Multi-Level Approach to NBTI Mitigation in Processors

“…We model a 4-wide issue core, which is similar to those in multicore processors. We assume the initial threshold voltage of the PMOS devices in the memory cells to be 0.2 V and the service life of the processor to be 7 years based on the work by Tiwari and Torrellas [15]. Previous work [18] has shown that, of these three metrics, the SNM is the one that is most heavily affected by NBTI and therefore we use SNM as the reliability metric in this chapter.…”

“…Using RAMP, they show that dynamic voltage scaling is an effective response technique for DRM, and that dynamic thermal management neither subsumes nor is subsumed by DRM. Tiwari and Torrellas propose a technique called "Facelift" [15] to hide the effects of aging through temperature-based job-scheduling to individual cores of a multicore processor. Facelift hides the effects of aging by steering hightemperature jobs to the fast cores and low-temperature jobs to the slow cores.…”