Enhancing the L1 Data Cache Design to Mitigate HCI

Valero, Alejandro; Miralaei, Negar; Petit, Salvador; Sahuquillo, Julio; Jones, Timothy M.

doi:10.1109/lca.2015.2460736

Cited by 2 publications

(1 citation statement)

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“…Overall, the percentage of zero bytes is on average by 51% 1 . Based on these results, simply skipping the writing of zero byte values to the cache and maintaining the previously cached byte could reduce the amount of time that the memory cells contain a logic '0' value [15]. However, this may imply storing '1' for longer periods of time, which would speed up BTI in transistors T P2 and T N1 .…”

Section: B Bti Mitigation: the Szb Mechanismmentioning

confidence: 99%

On Microarchitectural Mechanisms for Cache Wearout Reduction

Valero

Miralaei

Petit

et al. 2017

IEEE Trans. VLSI Syst.

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Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic '0' to '1' and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especially acute in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical for performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon previous studies showing that logic '0' is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this work introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic '0' values are stored in the cells by switching off specific data bytes. Experimental results show that the threshold voltage degradation savings range from 21.8% to 44.3% depending on the application.

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Section: B Bti Mitigation: the Szb Mechanismmentioning

confidence: 99%