Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

Tsang, P. J.; Ogura, S.; Walker, William W.; Shepard, J.; Critchlow, D.L.

doi:10.1109/t-ed.1982.20748

Cited by 117 publications

(11 citation statements)

References 8 publications

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“…More extensive applications of spacers can be found in MOS technology. In the lightly doped drain-source (LDD) FET structure, spacers are used as an ion-implant mask to achieve a double-diffused structure that shows significant improvements in breakdown voltages, hot-electron effects, and short-channel effects (2,16). The spacers are also widely used in the self-aligned silicide technology (3,4) to prevent bridging between the gate and source/drain during the silicide formation.…”

Section: A Tand T Bell Laboratories Assisted In Meeting the Publicati...mentioning

confidence: 99%

Sidewall Spacer Technology for MOS and Bipolar Devices

Dhong¹,

Petrillo²

1986

J. Electrochem. Soc.

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Chemical‐vapor‐deposited (CVD) oxide or nitride sidewall spacers formed at the edges of polysilicon lines by reactive ion etching (RIE) have important applications in both MOS and bipolar technology. In this paper, we present processing parameters that have to be understood and monitored for any successful sidewall spacer process and also report some of the inherent limitations of the spacer technology, an angular dependence of etch rate in reactive ion etching, and a new interpretation of RIE selectivity. The processing parameters that we studied experimentally are oxide etch uniformity, oxide‐to‐silicon selectivity; conformality, uniformity, and thickness of CVD deposition. The effects of these parameters on the shape of the spacers were noted and compared with computer simulation done by using the SAMPLE program. Good agreement between the experiments and computer modeling was only obtained when an angular dependence of etch rate in RIE was included in the computer model. The analytic and anisotropic etch models were inadequate in predicting the exact spacer shape but provided a sufficiently accurate first‐order approximation. Experiments also showed that oxide‐to‐silicon selectivity is a strong function of time that, as etching continues, asymptotically reaches the selectivity values previously reported in literature.

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Section: A Tand T Bell Laboratories Assisted In Meeting the Publicati...mentioning

confidence: 99%

Sidewall Spacer Technology for MOS and Bipolar Devices

Dhong¹,

Petrillo²

1986

J. Electrochem. Soc.

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“…As a rule it is associated with the appreciable outlay for hardware upgrade. Sometimes, however, a creative approach to the manufacturing issues like in the case of spacers [1,2], nanoribbons [3] or so-called lateral pattern definition technique [4,5] can make downsizing less expensive.…”

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confidence: 99%

Nanoscale Pattern Definition by Edge Oxidation of Silicon under the Si₃N₄mask - PaDEOx

et al. 2009

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Well-controlled method of Si nanopattern definition-pattern definition by edge oxidation have been presented. The technique is suitable for fabrication of narrow paths of width ranged from several tens of nm to several ľm by means of photolithography equipment working with ľm-scale design rules. Process details influencing a shape of the Si pattern have been discussed. SEM examinations have been presented.

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“…This was Paper 237 presented at the Philadelphia, PA, Meeting of the Society, May [10][11][12][13][14][15]1987.…”

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A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

Norström¹,

Nygren²,

Johansson³

et al. 2019

J. Electrochem. Soc.

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A polycide process with silicided diffusions is presented. This allows simultaneous use of mutually different silicides on the gate electrode and on the respective source and drain areas. The novel technique was used to fabricate MOSFETs and TiSi~/poly-Si gate electrodes and self-aligned PtSi on source/drain regions. Respective sheet resistivities were 5 and 7-812/[3 and no degradation effects were observed. A comparison with the more conventional salicide concept is made and several advantages are elucidated.As integrated MOSFET dimensions are reduced, contact and interconnection parasitics tend to become more important and will ultimately limit overall circuit performance. Novel or modified processes have therefore been proposed to overcome or alleviate these effects. In the polycide configuration (1) the polycrystalline silicon on the gate level is shunted by a silicide overlayer in order to reduce RC time constants and IR voltage drops. This layer is normally deposited prior to source/drain formation and must be stable at temperatures around 900~ For this reason, only refractory silicides (e.g., WSi2, MoSi2, TaSi2, or TiSi2) have been seriously considered for this application. A silicide top layer may reduce the sheet resistivity by a factor of 10-20 relative to a single layer of doped polysilicon.More recently, low resistive coatings have also been proposed for the source/drain diffusions, as corresponding sheet resistivities increase due to reduced junction depths. It has been suggested that a shunt layer could reduce the parasitic series resistance and relax the misalignment sensitivity. In the so-called salicide (self-aligned silicide) technique (2) a silicide is formed on exposed silicon regions by direct reaction with a deposited metal. Thus the source/ drain areas and the gate level interconnections are simultaneously silicided without any additional photo masking step. Unreacted metal on oxide-masked regions is subsequently removed in a selective wet etch. Self-aligned formation of platinum silicide is a well-established technique that has been in use for a long time (3). As metal atoms are the dominant diffusing species in the formation of this silicide, very good selectivity with minimal lateral growth can be achieved. For MOS applications according to the salicide concept, the disilicides of titanium (4) and cobalt (5) have been, however, most thoroughly studied.Two major constraints inherent to the sa[icide method are eliminated in the process to be described in this paper:1. The same silicide and the same layer thickness is used on the gate electrode and on the source/drain regions. Consequently, respective metallizations cannot be individually optimized, but a compromise has to be made. * Electrochemical Society Active Member. 1 Present Address: IMEC Laboratory, B-3030 Leuven, Belgium.2. Great care has to be taken to prevent short circuits between the gate electrode and the source/drain regions. As these are separated by dielectric spacers only a few tenths of a micron wide, lateral silicide gro...

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Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

Cited by 117 publications

References 8 publications

Sidewall Spacer Technology for MOS and Bipolar Devices

Sidewall Spacer Technology for MOS and Bipolar Devices

Nanoscale Pattern Definition by Edge Oxidation of Silicon under the Si₃N₄mask - PaDEOx

A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

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Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

Cited by 117 publications

References 8 publications

Sidewall Spacer Technology for MOS and Bipolar Devices

Sidewall Spacer Technology for MOS and Bipolar Devices

Nanoscale Pattern Definition by Edge Oxidation of Silicon under the Si3N4mask - PaDEOx

A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

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Product

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Nanoscale Pattern Definition by Edge Oxidation of Silicon under the Si₃N₄mask - PaDEOx