Sidewall Spacer Technology for MOS and Bipolar Devices

Abstract

Chemical‐vapor‐deposited (CVD) oxide or nitride sidewall spacers formed at the edges of polysilicon lines by reactive ion etching (RIE) have important applications in both MOS and bipolar technology. In this paper, we present processing parameters that have to be understood and monitored for any successful sidewall spacer process and also report some of the inherent limitations of the spacer technology, an angular dependence of etch rate in reactive ion etching, and a new interpretation of RIE selectivity. The processing parameters that we studied experimentally are oxide etch uniformity, oxide‐to‐silicon selectivity; conformality, uniformity, and thickness of CVD deposition. The effects of these parameters on the shape of the spacers were noted and compared with computer simulation done by using the SAMPLE program. Good agreement between the experiments and computer modeling was only obtained when an angular dependence of etch rate in RIE was included in the computer model. The analytic and anisotropic etch models were inadequate in predicting the exact spacer shape but provided a sufficiently accurate first‐order approximation. Experiments also showed that oxide‐to‐silicon selectivity is a strong function of time that, as etching continues, asymptotically reaches the selectivity values previously reported in literature.

Oxide Passivation of Photochemically Unpinned GaAs

“…Thus, the following picture of the oxide growth process emerges (6,9,10). GaAs is oxidized through the availability of minority carriers and water.…”