A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

Abstract

A polycide process with silicided diffusions is presented. This allows simultaneous use of mutually different silicides on the gate electrode and on the respective source and drain areas. The novel technique was used to fabricate MOSFETs and TiSi~/poly-Si gate electrodes and self-aligned PtSi on source/drain regions. Respective sheet resistivities were 5 and 7-812/[3 and no degradation effects were observed. A comparison with the more conventional salicide concept is made and several advantages are elucidated.As integrated MOSFET dimensions are reduced, contact and interconnection parasitics tend to become more important and will ultimately limit overall circuit performance. Novel or modified processes have therefore been proposed to overcome or alleviate these effects. In the polycide configuration (1) the polycrystalline silicon on the gate level is shunted by a silicide overlayer in order to reduce RC time constants and IR voltage drops. This layer is normally deposited prior to source/drain formation and must be stable at temperatures around 900~ For this reason, only refractory silicides (e.g., WSi2, MoSi2, TaSi2, or TiSi2) have been seriously considered for this application. A silicide top layer may reduce the sheet resistivity by a factor of 10-20 relative to a single layer of doped polysilicon.More recently, low resistive coatings have also been proposed for the source/drain diffusions, as corresponding sheet resistivities increase due to reduced junction depths. It has been suggested that a shunt layer could reduce the parasitic series resistance and relax the misalignment sensitivity. In the so-called salicide (self-aligned silicide) technique (2) a silicide is formed on exposed silicon regions by direct reaction with a deposited metal. Thus the source/ drain areas and the gate level interconnections are simultaneously silicided without any additional photo masking step. Unreacted metal on oxide-masked regions is subsequently removed in a selective wet etch. Self-aligned formation of platinum silicide is a well-established technique that has been in use for a long time (3). As metal atoms are the dominant diffusing species in the formation of this silicide, very good selectivity with minimal lateral growth can be achieved. For MOS applications according to the salicide concept, the disilicides of titanium (4) and cobalt (5) have been, however, most thoroughly studied.Two major constraints inherent to the sa[icide method are eliminated in the process to be described in this paper:1. The same silicide and the same layer thickness is used on the gate electrode and on the source/drain regions. Consequently, respective metallizations cannot be individually optimized, but a compromise has to be made. * Electrochemical Society Active Member. 1 Present Address: IMEC Laboratory, B-3030 Leuven, Belgium.2. Great care has to be taken to prevent short circuits between the gate electrode and the source/drain regions. As these are separated by dielectric spacers only a few tenths of a micron wide, lateral silicide gro...